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10469 Commits (22771dd2dd804b08ccd37d8d6f85888dfbbba111)
 

Author SHA1 Message Date
Scott Lahteine 22771dd2dd Update 'board_f_cpu' to 'board_build.f_cpu'
Scott Lahteine 6775a16c97 Fix switching extruder stepping with LA
Scott Lahteine 05fc761929
Merge pull request from thinkyhead/bf2_rename_some_options 
[2.0.x] Rename and document some configuration options
Scott Lahteine 2e139fe50f Tweak configuration spacing
Scott Lahteine 931ab4ec40 Rename Junction Deviation options
Scott Lahteine aaaf09bda2 BEZIER_JERK_CONTROL => S_CURVE_ACCELERATION
Scott Lahteine cf7d5a642a
Fix manual moves for switching tools ()
Eduardo José Tagle 1da2c4f1c1 Text LCD display routine fix. Coauthored with @MagoKimbra ()
Bob Kuhn 498a328148
Merge pull request from Bob-the-Kuhn/upload-extra-script-fix 
[2.0.x] LPC1768 upload_extra_script.py fix (wrong type of exit method)
Bob-the-Kuhn 1c0ad8bbae wrong type of exit method
Scott Lahteine 01d37e00af
Fix up stepper ISR with linear advance timing () 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
Eduardo José Tagle 6f330f397e [2.0.x] Buffer overflow and scroll fix, UTF8 cleanup ()
Bob Kuhn 235facd545 install AVRDUDE 5.10, faster disk find for LPC1768 ()
Scott Lahteine 645df23eb0 Fix warning with FASTER_GCODE_PARSER disabled
Scott Lahteine d74e333c0f Make sure FAN_ANIM_FRAMES is defined
Bob Kuhn e2db509d58 [2.0.x] Update/Fix LPC1768 extra script upload_extra_script.py () 
* Use a different method to find the volume info in Windows
Scott Lahteine 7261f48872 Fix reset of endstops and move state
Scott Lahteine 50fa8e01c1 Minor optimization of axis_did_move bits
Scott Lahteine a94506ada0 Fix K8400 Y min pos, M118 comment
Scott Lahteine 336a022529 Support Malyan LCD without SD
Scott Lahteine f28e366b77 Followup for core endstops
Scott Lahteine 8b44745bc7
Clean up and consolidate SD-related code ()
Scott Lahteine 9644d56b42 Patches for core motion tests
Scott Lahteine 5f8591528e Remove #pragmas that don't help c files
Scott Lahteine 230ae6a143 Default G30 to engage / disengage
Scott Lahteine 3e3789da85
Regression: Endstops Core compatibility () 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
Scott Lahteine c89649b46e Suppress U8glib build warnings
Axel bbd09a99f1 32 bit boards classification cleanup () 
- Ordering and match classification between `boards.h` and `pins.h`
- Check `pins.h` environments
Scott Lahteine ee333f6be2 Followup to endstops tweaks
Axel d98bc71af7 Boards classification arrangement () 
STM32 ARM Cortex-M3 boards were listed as M4
Bob Kuhn 22e0691a70 [2.0.x] Add Sublime support for Auto build, minor Auto-build update ()
Scott Lahteine 4b610b333e Tweak G38 formatting
Scott Lahteine d2647c1f19 Fix G1 behaviour after tool unpark 
Fix  for 2.0.x

Co-Authored-By: Ante Vukorepa <o.orcinus@gmail.com>
Scott Lahteine 3bb950c69a Fix DEBUG_LEVELING_FEATURE for MBL 
As noted in
Scott Lahteine 1af98519cd Group and adjust LCD buttons code
Scott Lahteine 0c3773d724 Cleanup in stepper_indirection.h
Scott Lahteine 4118199ddd Tweaks to core headers
Scott Lahteine 4b2f6e3b2b
[2.0.x] Add endstop noise filter ()
Scott Lahteine 65a004564c Stepper::set_position needed for some applications
Scott Lahteine 435ecb6b67 Followup to stepper/planner refactor
Bob Kuhn 6dfbb39f83 [LPC1768] Add error-handling to upload script, update autobuild.py ()
Scott Lahteine 68d7fcec83 Simplify and fix Z fade height edit 
Fix
Bob Kuhn d557c84a71 [2.0.x] Error for FAST_PWM_FAN with 32 bit CPU ()
Scott Lahteine 16f92dca44
Merge pull request from ejtagle/bugfix-2.0.x 
[2.0.x] Refactor, optimization of core planner/stepper/endstops logic
etagle 569df3fc0c Fix interrupt-based endstop detection 
- Also implemented real endstop reading on interrupt.
etagle a4af975873 Fix planner block optimization 
- Fixed the planner incorrectly avoiding optimization of the block following the active one.
- Added extra conditions to terminate planner early and avoid redundant computations.
etagle e0ca627033 Planner block HOLD flag 
Allows the Stepper ISR to wait until a given block is free for use. Allows Planner to plan the first move, which is split into two.
etagle a11eb50a3e Refactor and optimize Stepper/Planner 
Better encapsulation and considerably reduce stepper jitter
etagle 0566badcef Add memory barrier, optimal interrupt on-off 
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
Scott Lahteine c2fb2f54a1 Use assembly for AVR ISR vectors 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>