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@ -258,6 +258,11 @@ bool LPC1768_PWM_attach_pin(pin_t pin, uint32_t min /* = 1 */, uint32_t max /* =
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// OK to update the active table because the
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// ISR doesn't use any of the changed items
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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if (ISR_table_update) //use work table if that's the newest
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temp_table = work_table;
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else
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@ -342,6 +347,11 @@ bool LPC1768_PWM_detach_pin(pin_t pin) {
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//// interrupt controlled PWM code
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NVIC_DisableIRQ(HAL_PWM_TIMER_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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if (ISR_table_update) {
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ISR_table_update = false; // don't update yet - have another update to do
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NVIC_EnableIRQ(HAL_PWM_TIMER_IRQn); // re-enable PWM interrupts
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@ -428,6 +438,12 @@ bool LPC1768_PWM_write(pin_t pin, uint32_t value) {
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//// interrupt controlled PWM code
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NVIC_DisableIRQ(HAL_PWM_TIMER_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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if (!ISR_table_update) // use the most up to date table
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COPY_ACTIVE_TABLE; // copy active table into work table
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@ -456,6 +472,11 @@ bool useable_hardware_PWM(pin_t pin) {
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NVIC_DisableIRQ(HAL_PWM_TIMER_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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bool return_flag = false;
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for (uint8_t i = 0; i < NUM_ISR_PWMS; i++) // see if it's already setup
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if (active_table[i].pin == pin) return_flag = true;
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