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@ -20,42 +20,38 @@
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*
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*/
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/*
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u8g_dev_ssd1306_128x64.c
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Universal 8bit Graphics Library
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Copyright (c) 2011, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* Based on u8g_dev_ssd1306_128x64.c
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*
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* Universal 8bit Graphics Library
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*
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* Copyright (c) 2015, olikraus@gmail.com
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* These routines are meant for two wire I2C interfaces.
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@ -85,43 +81,38 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
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// The sh1106 is compatible to the ssd1306, but is 132x64. 128x64 display area is centered within
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// the 132x64.
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static const uint8_t u8g_dev_sh1106_128x64_data_start_2_wire[] PROGMEM = {
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0x010, // set upper 4 bit of the col adr to 0
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0x002, // set lower 4 bit of the col adr to 2 (centered display with ssd1306)
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U8G_ESC_END // end of sequence
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};
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static const uint8_t u8g_dev_sh1106_128x64_init_seq_2_wire[] PROGMEM = {
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U8G_ESC_ADR(0), // initiate command mode
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0x0ae, /* display off, sleep mode */
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0x0a8, 0x03f, /* mux ratio */
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0x0d3, 0x00, /* display offset */
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0x040, /* start line */
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0x0a1, /* segment remap a0/a1*/
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0x0c8, /* c0: scan dir normal, c8: reverse */
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0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
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0x081, 0x0cf, /* [2] set contrast control */
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0x020, 0x002, /* 2012-05-27: page addressing mode */
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0x0AE, // display off, sleep mode
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0x0A8, 0x03F, // mux ratio
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0x0D3, 0x00, // display offset
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0x040, // start line
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0x0A1, // segment remap a0/a1
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0x0C8, // c0: scan dir normal, c8: reverse
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0x0DA, 0x012, // com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
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0x081, 0x0CF, // [2] set contrast control
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0x020, 0x002, // 2012-05-27: page addressing mode
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0x21, 2, 0x81, // set column range from 0 through 131
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0x22, 0, 7, // set page range from 0 through 7
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0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
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0x0db, 0x040, /* vcomh deselect level */
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0x0a4, /* output ram to display */
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0x0a6, /* none inverted normal display mode */
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0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
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0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
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0x02e, /* 2012-05-27: Deactivate scroll */
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0x0af, /* display on */
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U8G_ESC_END /* end of sequence */
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0x0D9, 0x0F1, // [2] pre-charge period 0x022/f1
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0x0DB, 0x040, // vcomh deselect level
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0x0A4, // output ram to display
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0x0A6, // none inverted normal display mode
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0x0D5, 0x080, // clock divide ratio (0x00=1) and oscillator frequency (0x8)
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0x08D, 0x014, // [2] charge pump setting (p62): 0x014 enable, 0x010 disable
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0x02E, // 2012-05-27: Deactivate scroll
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0x0AF, // display on
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U8G_ESC_END // end of sequence
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};
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uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
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switch(msg) {
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP_2_wire(u8g, dev, u8g_dev_sh1106_128x64_init_seq_2_wire);
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@ -152,7 +143,6 @@ uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t m
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return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
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}
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uint8_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf[WIDTH*2] U8G_NOCOMMON ;
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u8g_pb_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf};
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u8g_dev_t u8g_dev_sh1106_128x64_2x_i2c_2_wire = { u8g_dev_sh1106_128x64_2x_2_wire_fn, &u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb, U8G_COM_SSD_I2C_HAL };
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@ -165,36 +155,32 @@ static const uint8_t u8g_dev_ssd1306_128x64_data_start_2_wire[] PROGMEM = {
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U8G_ESC_END // end of sequence
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};
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static const uint8_t u8g_dev_ssd1306_128x64_init_seq_2_wire[] PROGMEM = {
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U8G_ESC_ADR(0), // initiate command mode
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0x0ae, /* display off, sleep mode */
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0x0a8, 0x03f, /* mux ratio */
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0x0d3, 0x00, /* display offset */
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0x040, /* start line */
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0x0a1, /* segment remap a0/a1*/
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0x0c8, /* c0: scan dir normal, c8: reverse */
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0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
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0x081, 0x0cf, /* [2] set contrast control */
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0x020, 0x002, /* 2012-05-27: page addressing mode */
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0x21, 0, 0x7f, // set column range from 0 through 127
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0x0AE, // display off, sleep mode
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0x0A8, 0x03F, // mux ratio
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0x0D3, 0x00, // display offset
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0x040, // start line
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0x0A1, // segment remap a0/a1
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0x0C8, // c0: scan dir normal, c8: reverse
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0x0DA, 0x012, // com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
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0x081, 0x0CF, // [2] set contrast control
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0x020, 0x002, // 2012-05-27: page addressing mode
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0x21, 0, 0x7F, // set column range from 0 through 127
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0x22, 0, 7, // set page range from 0 through 7
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0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
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0x0db, 0x040, /* vcomh deselect level */
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0x0a4, /* output ram to display */
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0x0a6, /* none inverted normal display mode */
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0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
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0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
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0x02e, /* 2012-05-27: Deactivate scroll */
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0x0af, /* display on */
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U8G_ESC_END /* end of sequence */
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0x0D9, 0x0F1, // [2] pre-charge period 0x022/f1
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0x0DB, 0x040, // vcomh deselect level
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0x0A4, // output ram to display
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0x0A6, // none inverted normal display mode
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0x0D5, 0x080, // clock divide ratio (0x00=1) and oscillator frequency (0x8)
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0x08D, 0x014, // [2] charge pump setting (p62): 0x014 enable, 0x010 disable
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0x02E, // 2012-05-27: Deactivate scroll
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0x0AF, // display on
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U8G_ESC_END // end of sequence
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};
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uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
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switch(msg) {
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP_2_wire(u8g, dev, u8g_dev_ssd1306_128x64_init_seq_2_wire);
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@ -238,54 +224,42 @@ u8g_dev_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire = { u8g_dev_ssd1306_128x64_2x_2_w
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#define I2C_CMD_MODE 0x080
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uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq)
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{
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uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq) {
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uint8_t is_escape = 0;
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uint8_t value;
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for(;;)
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{
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for(;;) {
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value = u8g_pgm_read(esc_seq);
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if ( is_escape == 0 )
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{
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if ( value != 255 )
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{
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if ( u8g_WriteByte(u8g, dev, value) == 0 )
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if (is_escape == 0) {
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if (value != 255) {
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if (u8g_WriteByte(u8g, dev, value) == 0 )
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return 0;
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if ( u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
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if (u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
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return 0;
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}
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else
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{
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else {
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is_escape = 1;
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}
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}
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else
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{
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if ( value == 255 )
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{
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if ( u8g_WriteByte(u8g, dev, value) == 0 )
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else {
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if (value == 255) {
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if (u8g_WriteByte(u8g, dev, value) == 0 )
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return 0;
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if ( u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
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if (u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
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return 0;
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}
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else if ( value == 254 )
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{
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else if (value == 254) {
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break;
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}
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else if ( value >= 0x0f0 )
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{
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else if (value >= 0x0f0) {
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/* not yet used, do nothing */
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}
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else if ( value >= 0xe0 )
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{
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else if (value >= 0xe0 ) {
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u8g_SetAddress(u8g, dev, value & 0x0f);
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}
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else if ( value >= 0xd0 )
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{
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else if (value >= 0xd0) {
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u8g_SetChipSelect(u8g, dev, value & 0x0f);
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}
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else if ( value >= 0xc0 )
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{
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else if (value >= 0xc0) {
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u8g_SetResetLow(u8g, dev);
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value &= 0x0f;
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value <<= 4;
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@ -294,13 +268,10 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
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u8g_SetResetHigh(u8g, dev);
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u8g_Delay(value);
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}
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else if ( value >= 0xbe )
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{
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/* not yet implemented */
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else if (value >= 0xbe) { /* not yet implemented */
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/* u8g_SetVCC(u8g, dev, value & 0x01); */
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}
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else if ( value <= 127 )
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{
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else if (value <= 127) {
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u8g_Delay(value);
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}
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is_escape = 0;
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Scott Lahteine
7 years ago