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@ -47,12 +47,7 @@
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#warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
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#warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
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#endif
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#endif
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struct spi_pins {
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struct spi_pins { uint8_t nss, sck, miso, mosi; };
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uint8_t nss;
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uint8_t sck;
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uint8_t miso;
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uint8_t mosi;
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};
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static const spi_pins* dev_to_spi_pins(spi_dev *dev);
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static const spi_pins* dev_to_spi_pins(spi_dev *dev);
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static void configure_gpios(spi_dev *dev, bool as_master);
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static void configure_gpios(spi_dev *dev, bool as_master);
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@ -84,20 +79,20 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
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};
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};
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#if BOARD_NR_SPI >= 1
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#if BOARD_NR_SPI >= 1
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static void (*_spi1_this);
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static void *_spi1_this;
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#endif
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#endif
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#if BOARD_NR_SPI >= 2
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#if BOARD_NR_SPI >= 2
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static void (*_spi2_this);
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static void *_spi2_this;
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#endif
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#endif
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#if BOARD_NR_SPI >= 3
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#if BOARD_NR_SPI >= 3
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static void (*_spi3_this);
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static void *_spi3_this;
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#endif
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#endif
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/**
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/**
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* Constructor
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* Constructor
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*/
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*/
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SPIClass::SPIClass(uint32_t spi_num) {
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SPIClass::SPIClass(uint32_t spi_num) {
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_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
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_currentSetting = &_settings[spi_num - 1]; // SPI channels are called 1 2 and 3 but the array is zero indexed
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switch (spi_num) {
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switch (spi_num) {
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#if BOARD_NR_SPI >= 1
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#if BOARD_NR_SPI >= 1
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@ -149,7 +144,7 @@ SPIClass::SPIClass(uint32_t spi_num) {
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_currentSetting->state = SPI_STATE_IDLE;
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_currentSetting->state = SPI_STATE_IDLE;
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}
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}
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/*
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/**
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* Set up/tear down
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* Set up/tear down
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*/
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*/
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void SPIClass::updateSettings() {
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void SPIClass::updateSettings() {
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@ -175,8 +170,7 @@ void SPIClass::beginSlave() {
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}
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}
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void SPIClass::end() {
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void SPIClass::end() {
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if (!spi_is_enabled(_currentSetting->spi_d))
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if (!spi_is_enabled(_currentSetting->spi_d)) return;
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return;
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// Follows RM0008's sequence for disabling a SPI in master/slave
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// Follows RM0008's sequence for disabling a SPI in master/slave
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// full duplex mode.
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// full duplex mode.
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@ -184,8 +178,8 @@ void SPIClass::end() {
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// FIXME [0.1.0] remove this once you have an interrupt based driver
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// FIXME [0.1.0] remove this once you have an interrupt based driver
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volatile uint16_t rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
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volatile uint16_t rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
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}
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}
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while (!spi_is_tx_empty(_currentSetting->spi_d)) {};
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while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ }
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while (spi_is_busy(_currentSetting->spi_d)) {};
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while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ }
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spi_peripheral_disable(_currentSetting->spi_d);
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spi_peripheral_disable(_currentSetting->spi_d);
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// added for DMA callbacks.
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// added for DMA callbacks.
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@ -207,10 +201,10 @@ void SPIClass::setBitOrder(BitOrder bitOrder) {
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_currentSetting->spi_d->regs->CR1 = cr1;
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_currentSetting->spi_d->regs->CR1 = cr1;
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}
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}
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/* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
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/**
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* Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
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* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
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*
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* Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
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*/
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*/
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void SPIClass::setDataSize(uint32_t datasize) {
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void SPIClass::setDataSize(uint32_t datasize) {
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_currentSetting->dataSize = datasize;
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_currentSetting->dataSize = datasize;
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uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
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uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
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@ -220,9 +214,11 @@ void SPIClass::setDataSize(uint32_t datasize) {
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}
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}
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void SPIClass::setDataMode(uint8_t dataMode) {
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void SPIClass::setDataMode(uint8_t dataMode) {
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/* Notes:
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/*
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As far as I can tell, the AVR numbers for dataMode appear to match the numbers required by the STM32
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Notes:
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As far as we know the AVR numbers for dataMode match the numbers required by the STM32.
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From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
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From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
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SPI Mode CPOL CPHA Shift SCK-edge Capture SCK-edge
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SPI Mode CPOL CPHA Shift SCK-edge Capture SCK-edge
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0 0 0 Falling Rising
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0 0 0 Falling Rising
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1 0 1 Rising Falling
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1 0 1 Rising Falling
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@ -265,13 +261,12 @@ void SPIClass::beginTransactionSlave(SPISettings settings) {
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void SPIClass::endTransaction() { }
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void SPIClass::endTransaction() { }
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/**
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/*
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* I/O
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* I/O
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*/
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*/
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uint16_t SPIClass::read() {
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uint16_t SPIClass::read() {
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while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
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while (!spi_is_rx_nonempty(_currentSetting->spi_d)) { /* nada */ }
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return (uint16)spi_rx_reg(_currentSetting->spi_d);
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return (uint16)spi_rx_reg(_currentSetting->spi_d);
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}
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}
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@ -282,16 +277,16 @@ void SPIClass::read(uint8_t *buf, uint32_t len) {
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// start sequence: write byte 0
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// start sequence: write byte 0
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regs->DR = 0x00FF; // write the first byte
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regs->DR = 0x00FF; // write the first byte
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// main loop
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// main loop
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while ( (--len) ) {
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while (--len) {
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while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag
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while(!(regs->SR & SPI_SR_TXE)) { /* nada */ } // wait for TXE flag
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noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data
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noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data
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regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
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regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
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while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register
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while (!(regs->SR & SPI_SR_RXNE)) { /* nada */ } // wait till data is available in the DR register
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*buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
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*buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
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interrupts(); // let systick do its job
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interrupts(); // let systick do its job
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}
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}
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// read remaining last byte
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// read remaining last byte
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while ( !(regs->SR & SPI_SR_RXNE) ) {} // wait till data is available in the Rx register
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while (!(regs->SR & SPI_SR_RXNE)) { /* nada */ } // wait till data is available in the Rx register
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*buf++ = (uint8)(regs->DR); // read and store the received byte
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*buf++ = (uint8)(regs->DR); // read and store the received byte
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}
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}
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@ -302,42 +297,42 @@ void SPIClass::write(uint16_t data) {
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* This almost doubles the speed of this function.
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* This almost doubles the speed of this function.
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*/
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*/
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spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
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while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
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}
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}
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void SPIClass::write16(uint16_t data) {
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void SPIClass::write16(uint16_t data) {
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// Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
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// Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
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spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
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spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
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while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
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while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // Wait until TXE=1
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spi_tx_reg(_currentSetting->spi_d, data); // write low byte
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spi_tx_reg(_currentSetting->spi_d, data); // write low byte
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while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
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while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // Wait until TXE=1
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while (spi_is_busy(_currentSetting->spi_d) != 0); // wait until BSY=0
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while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // wait until BSY=0
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}
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}
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void SPIClass::write(uint16_t data, uint32_t n) {
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void SPIClass::write(uint16_t data, uint32_t n) {
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// Added by stevstrong: Repeatedly send same data by the specified number of times
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// Added by stevstrong: Repeatedly send same data by the specified number of times
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spi_reg_map * regs = _currentSetting->spi_d->regs;
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spi_reg_map * regs = _currentSetting->spi_d->regs;
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while ( (n--)>0 ) {
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while (n--) {
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regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
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while (!(regs->SR & SPI_SR_TXE)) { /* nada */ } // wait till Tx empty
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}
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}
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while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning
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while (regs->SR & SPI_SR_BSY) { /* nada */ } // wait until BSY=0 before returning
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}
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}
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void SPIClass::write(const void *data, uint32_t length) {
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void SPIClass::write(const void *data, uint32_t length) {
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_tx(spi_d, data, length); // data can be array of bytes or words
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spi_tx(spi_d, data, length); // data can be array of bytes or words
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (!spi_is_tx_empty(spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
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while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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while (spi_is_busy(spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
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}
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}
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uint8_t SPIClass::transfer(uint8_t byte) const {
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uint8_t SPIClass::transfer(uint8_t byte) const {
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_rx_reg(spi_d); // read any previous data
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spi_rx_reg(spi_d); // read any previous data
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spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
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spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (!spi_is_tx_empty(spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
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while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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while (spi_is_busy(spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
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return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
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return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
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}
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}
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@ -347,22 +342,23 @@ uint16_t SPIClass::transfer16(uint16_t data) const {
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_rx_reg(spi_d); // read any previous data
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spi_rx_reg(spi_d); // read any previous data
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spi_tx_reg(spi_d, data>>8); // write high byte
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spi_tx_reg(spi_d, data>>8); // write high byte
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while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
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while (!spi_is_tx_empty(spi_d)) { /* nada */ } // wait until TXE=1
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while (spi_is_busy(spi_d) != 0); // wait until BSY=0
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while (spi_is_busy(spi_d)) { /* nada */ } // wait until BSY=0
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uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte
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uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte
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spi_tx_reg(spi_d, data); // write low byte
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spi_tx_reg(spi_d, data); // write low byte
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while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
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while (!spi_is_tx_empty(spi_d)) { /* nada */ } // wait until TXE=1
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|
|
|
while (spi_is_busy(spi_d) != 0); // wait until BSY=0
|
|
|
|
while (spi_is_busy(spi_d)) { /* nada */ } // wait until BSY=0
|
|
|
|
ret += spi_rx_reg(spi_d); // read low byte
|
|
|
|
ret += spi_rx_reg(spi_d); // read low byte
|
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|
return ret;
|
|
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|
return ret;
|
|
|
|
}
|
|
|
|
}
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|
|
|
|
|
|
|
|
|
|
/* Roger Clark and Victor Perez, 2015
|
|
|
|
/**
|
|
|
|
* Performs a DMA SPI transfer with at least a receive buffer.
|
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|
* Roger Clark and Victor Perez, 2015
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|
* If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer.
|
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|
* Performs a DMA SPI transfer with at least a receive buffer.
|
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|
|
* On exit TX buffer is not modified, and RX buffer cotains the received data.
|
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|
* If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer.
|
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|
* Still in progress.
|
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|
|
* On exit TX buffer is not modified, and RX buffer cotains the received data.
|
|
|
|
*/
|
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|
* Still in progress.
|
|
|
|
|
|
|
|
*/
|
|
|
|
void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
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|
|
void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
|
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|
|
dma_init(_currentSetting->spiDmaDev);
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|
dma_init(_currentSetting->spiDmaDev);
|
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|
//spi_rx_dma_enable(_currentSetting->spi_d);
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|
//spi_rx_dma_enable(_currentSetting->spi_d);
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|
@ -399,13 +395,13 @@ uint8_t SPIClass::dmaTransferRepeat(uint16_t length) {
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|
//uint32_t m = millis();
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|
//uint32_t m = millis();
|
|
|
|
uint8_t b = 0;
|
|
|
|
uint8_t b = 0;
|
|
|
|
uint32_t m = millis();
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|
uint32_t m = millis();
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|
|
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1) == 0) {
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|
while (!(dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)) {
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|
|
//Avoid interrupts and just loop waiting for the flag to be set.
|
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|
|
// Avoid interrupts and just loop waiting for the flag to be set.
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|
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
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|
|
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
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|
|
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
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|
|
while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_rx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_rx_dma_disable(_currentSetting->spi_d);
|
|
|
|
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
@ -416,7 +412,8 @@ uint8_t SPIClass::dmaTransferRepeat(uint16_t length) {
|
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|
|
return b;
|
|
|
|
return b;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Roger Clark and Victor Perez, 2015
|
|
|
|
/**
|
|
|
|
|
|
|
|
* Roger Clark and Victor Perez, 2015
|
|
|
|
* Performs a DMA SPI transfer with at least a receive buffer.
|
|
|
|
* Performs a DMA SPI transfer with at least a receive buffer.
|
|
|
|
* If a TX buffer is not provided, FF is sent over and over for the length of the transfer.
|
|
|
|
* If a TX buffer is not provided, FF is sent over and over for the length of the transfer.
|
|
|
|
* On exit TX buffer is not modified, and RX buffer contains the received data.
|
|
|
|
* On exit TX buffer is not modified, and RX buffer contains the received data.
|
|
|
@ -427,7 +424,8 @@ uint8_t SPIClass::dmaTransfer(const void *transmitBuf, void *receiveBuf, uint16_
|
|
|
|
return dmaTransferRepeat(length);
|
|
|
|
return dmaTransferRepeat(length);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Roger Clark and Victor Perez, 2015
|
|
|
|
/**
|
|
|
|
|
|
|
|
* Roger Clark and Victor Perez, 2015
|
|
|
|
* Performs a DMA SPI send using a TX buffer.
|
|
|
|
* Performs a DMA SPI send using a TX buffer.
|
|
|
|
* On exit TX buffer is not modified.
|
|
|
|
* On exit TX buffer is not modified.
|
|
|
|
* Still in progress.
|
|
|
|
* Still in progress.
|
|
|
@ -448,19 +446,18 @@ uint8_t SPIClass::dmaSendRepeat(uint16_t length) {
|
|
|
|
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
|
|
|
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
|
|
|
_currentSetting->state = SPI_STATE_TRANSMIT;
|
|
|
|
_currentSetting->state = SPI_STATE_TRANSMIT;
|
|
|
|
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
|
|
|
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); // enable transmit
|
|
|
|
spi_tx_dma_enable(_currentSetting->spi_d);
|
|
|
|
spi_tx_dma_enable(_currentSetting->spi_d);
|
|
|
|
if (_currentSetting->transmitCallback)
|
|
|
|
if (_currentSetting->transmitCallback) return 0;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
uint32_t m = millis();
|
|
|
|
uint32_t m = millis();
|
|
|
|
uint8_t b = 0;
|
|
|
|
uint8_t b = 0;
|
|
|
|
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
|
|
|
while (!(dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)) {
|
|
|
|
//Avoid interrupts and just loop waiting for the flag to be set.
|
|
|
|
// Avoid interrupts and just loop waiting for the flag to be set.
|
|
|
|
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
|
|
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
|
|
}
|
|
|
|
}
|
|
|
|
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
|
|
while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
@ -478,14 +475,14 @@ uint8_t SPIClass::dmaSendAsync(const void * transmitBuf, uint16_t length, bool m
|
|
|
|
|
|
|
|
|
|
|
|
if (_currentSetting->state != SPI_STATE_READY) {
|
|
|
|
if (_currentSetting->state != SPI_STATE_READY) {
|
|
|
|
uint32_t m = millis();
|
|
|
|
uint32_t m = millis();
|
|
|
|
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
|
|
|
while (!(dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)) {
|
|
|
|
//Avoid interrupts and just loop waiting for the flag to be set.
|
|
|
|
//Avoid interrupts and just loop waiting for the flag to be set.
|
|
|
|
//delayMicroseconds(10);
|
|
|
|
//delayMicroseconds(10);
|
|
|
|
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
|
|
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
|
|
while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
|
|
_currentSetting->state = SPI_STATE_READY;
|
|
|
|
_currentSetting->state = SPI_STATE_READY;
|
|
|
@ -575,11 +572,11 @@ void SPIClass::onTransmit(void(*callback)(void)) {
|
|
|
|
* during the initial setup and only set the callback to EventCallback if they are set.
|
|
|
|
* during the initial setup and only set the callback to EventCallback if they are set.
|
|
|
|
*/
|
|
|
|
*/
|
|
|
|
void SPIClass::EventCallback() {
|
|
|
|
void SPIClass::EventCallback() {
|
|
|
|
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
|
|
while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
|
|
|
|
while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0"
|
|
|
|
switch (_currentSetting->state) {
|
|
|
|
switch (_currentSetting->state) {
|
|
|
|
case SPI_STATE_TRANSFER:
|
|
|
|
case SPI_STATE_TRANSFER:
|
|
|
|
while (spi_is_rx_nonempty(_currentSetting->spi_d));
|
|
|
|
while (spi_is_rx_nonempty(_currentSetting->spi_d)) { /* nada */ }
|
|
|
|
_currentSetting->state = SPI_STATE_READY;
|
|
|
|
_currentSetting->state = SPI_STATE_READY;
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_tx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_rx_dma_disable(_currentSetting->spi_d);
|
|
|
|
spi_rx_dma_disable(_currentSetting->spi_d);
|
|
|
@ -718,10 +715,10 @@ static const spi_baud_rate baud_rates[8] __FLASH__ = {
|
|
|
|
SPI_BAUD_PCLK_DIV_256,
|
|
|
|
SPI_BAUD_PCLK_DIV_256,
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
/**
|
|
|
|
* Note: This assumes you're on a LeafLabs-style board
|
|
|
|
* Note: This assumes you're on a LeafLabs-style board
|
|
|
|
* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
|
|
|
|
* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
|
|
|
|
*/
|
|
|
|
*/
|
|
|
|
static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
|
|
|
|
static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
|
|
|
|
uint32_t clock = 0;
|
|
|
|
uint32_t clock = 0;
|
|
|
|
switch (rcc_dev_clk(dev->clk_id)) {
|
|
|
|
switch (rcc_dev_clk(dev->clk_id)) {
|
|
|
|