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@ -825,6 +825,11 @@
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#else // U8G compatible hardware SPI
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#else // U8G compatible hardware SPI
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#define SPI_MODE_0_DUE_HW 2 // DUE CPHA control bit is inverted
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#define SPI_MODE_1_DUE_HW 3
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#define SPI_MODE_2_DUE_HW 0
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#define SPI_MODE_3_DUE_HW 1
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void spiInit(uint8_t spiRate = 6 ) { // default to slowest rate if not specified)
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void spiInit(uint8_t spiRate = 6 ) { // default to slowest rate if not specified)
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// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
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// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
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int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
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int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
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@ -848,7 +853,7 @@
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SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PCSDEC | SPI_MR_MODFDIS;
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SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PCSDEC | SPI_MR_MODFDIS;
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/* SPI mode 0, 8 Bit data transfer, baud rate */
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/* SPI mode 0, 8 Bit data transfer, baud rate */
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SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | 1;
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SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | SPI_MODE_0_DUE_HW;
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}
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}
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static uint8_t spiTransfer(uint8_t data) {
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static uint8_t spiTransfer(uint8_t data) {
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