BigTree SKR Pro V1.1 board support (#14523)
Msq001
6 years ago
committed by
Scott Lahteine
parent
3a75342508
commit
439e28783b
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2019 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#ifndef TARGET_STM32F4
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#error "Oops! Select an STM32F4 board in 'Tools > Board.'"
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#endif
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#if HOTENDS > 3 || E_STEPPERS > 3
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#error "BIGTREE SKR Pro V1.1 supports up to 3 hotends / E-steppers."
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#endif
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#define BOARD_NAME "BIGTREE SKR Pro V1.1"
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#define EEPROM_EMULATED_WITH_SRAM
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//
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// Servos
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//
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#define SERVO0_PIN PA1
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//
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// Limit Switches
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//
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#define X_MIN_PIN PB10
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#define X_MAX_PIN PE15
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#define Y_MIN_PIN PE12
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#define Y_MAX_PIN PE10
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#define Z_MIN_PIN PG8
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#define Z_MAX_PIN PG5
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//
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// Z Probe must be this pins
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//
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#ifndef Z_MIN_PROBE_PIN
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#define Z_MIN_PROBE_PIN PA2
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#endif
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//
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// Steppers
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//
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#define X_STEP_PIN PE9
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#define X_DIR_PIN PF1
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#define X_ENABLE_PIN PF2
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#ifndef X_CS_PIN
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#define X_CS_PIN PA15
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#endif
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#define Y_STEP_PIN PE11
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#define Y_DIR_PIN PE8
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#define Y_ENABLE_PIN PD7
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#ifndef Y_CS_PIN
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#define Y_CS_PIN PB8
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#endif
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#define Z_STEP_PIN PE13
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#define Z_DIR_PIN PC2
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#define Z_ENABLE_PIN PC0
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#ifndef Z_CS_PIN
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#define Z_CS_PIN PB9
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#endif
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#define E0_STEP_PIN PE14
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#define E0_DIR_PIN PA0
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#define E0_ENABLE_PIN PC3
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#ifndef E0_CS_PIN
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#define E0_CS_PIN PB3
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#endif
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#define E1_STEP_PIN PD15
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#define E1_DIR_PIN PE7
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#define E1_ENABLE_PIN PA3
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#ifndef E1_CS_PIN
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#define E1_CS_PIN PG15
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#endif
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#define E2_STEP_PIN PD13
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#define E2_DIR_PIN PG9
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#define E2_ENABLE_PIN PF0
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#ifndef E2_CS_PIN
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#define E2_CS_PIN PG12
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#endif
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//
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// Software SPI pins for TMC2130 stepper drivers
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//
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#if ENABLED(TMC_USE_SW_SPI)
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#define TMC_SW_MOSI PC12
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#define TMC_SW_MISO PC11
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#define TMC_SW_SCK PC10
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#endif
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#if HAS_DRIVER(TMC2208)
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/**
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* TMC2208 stepper drivers
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*
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* Hardware serial communication ports.
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* If undefined software serial is used according to the pins below
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*/
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//#define X_HARDWARE_SERIAL Serial
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//#define X2_HARDWARE_SERIAL Serial1
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//#define Y_HARDWARE_SERIAL Serial1
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//#define Y2_HARDWARE_SERIAL Serial1
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//#define Z_HARDWARE_SERIAL Serial1
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//#define Z2_HARDWARE_SERIAL Serial1
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//#define E0_HARDWARE_SERIAL Serial1
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//#define E1_HARDWARE_SERIAL Serial1
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//#define E2_HARDWARE_SERIAL Serial1
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//#define E3_HARDWARE_SERIAL Serial1
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//#define E4_HARDWARE_SERIAL Serial1
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//
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// Software serial
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//
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#define X_SERIAL_TX_PIN PC13
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#define X_SERIAL_RX_PIN PE4
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#define Y_SERIAL_TX_PIN PE3
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#define Y_SERIAL_RX_PIN PE2
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#define Z_SERIAL_TX_PIN PE0
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#define Z_SERIAL_RX_PIN PE1
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#define E0_SERIAL_TX_PIN PD4
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#define E0_SERIAL_RX_PIN PD2
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#define E1_SERIAL_TX_PIN PD0
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#define E1_SERIAL_RX_PIN PD1
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#define Z2_SERIAL_TX_PIN PD6
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#define Z2_SERIAL_RX_PIN PD5
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#endif
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//
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// Temperature Sensors
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//
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#define TEMP_0_PIN PF3 // T0
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#define TEMP_1_PIN PF4 // T1
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#define TEMP_2_PIN PF5 // T2
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#define TEMP_BED_PIN PF6 // TB
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//
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// Heaters / Fans
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//
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#define HEATER_0_PIN PB1 // Heater0
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#define HEATER_1_PIN PD14 // Heater1
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#define HEATER_2_PIN PB0 // Heater1
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#define HEATER_BED_PIN PD12 // Hotbed
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#define FAN_PIN PC8 // Fan0
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#define FAN1_PIN PE5 // Fan1
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#define FAN2_PIN PE6 // Fan2
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//
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// Misc. Functions
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//
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#define SDSS PB12
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/*
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| _____ _____
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| NC | · · | GND 5V | · · | GND
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| RESET | · · | PF12(SD_DETECT) (LCD_D7) PG7 | · · | PG6 (LCD_D6)
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| (MOSI)PB15 | · · | PF11(BTN_EN2) (LCD_D5) PG3 | · · | PG2 (LCD_D4)
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| (SD_SS)PB12 | · · | PG10(BTN_EN1) (LCD_RS) PD10 | · · | PD11 (LCD_EN)
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| (SCK)PB13 | · · | PB14(MISO) (BTN_ENC) PA8 | · · | PG4 (BEEPER)
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| ￣￣ ￣￣
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| EXP2 EXP1
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*/
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#if HAS_SPI_LCD
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#define BEEPER_PIN PG4
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#define BTN_ENC PA8
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#if ENABLED(CR10_STOCKDISPLAY)
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#define LCD_PINS_RS PG6
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#define BTN_EN1 PD11
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#define BTN_EN2 PG2
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#define LCD_PINS_ENABLE PG7
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#define LCD_PINS_D4 PG3
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#else
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#define LCD_PINS_RS PD10
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#define BTN_EN1 PG10
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#define BTN_EN2 PF11
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#define SD_DETECT_PIN PF12
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#define LCD_SDSS PB12
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#define LCD_PINS_ENABLE PD11
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#define LCD_PINS_D4 PG2
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#if ENABLED(ULTIPANEL)
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#define LCD_PINS_D5 PG3
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#define LCD_PINS_D6 PG6
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#define LCD_PINS_D7 PG7
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#endif
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#endif
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// Alter timing for graphical display
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#if HAS_GRAPHICAL_DISPLAY
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#ifndef ST7920_DELAY_1
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#define ST7920_DELAY_1 DELAY_NS(96)
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#endif
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#ifndef ST7920_DELAY_2
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#define ST7920_DELAY_2 DELAY_NS(48)
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#endif
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#ifndef ST7920_DELAY_3
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#define ST7920_DELAY_3 DELAY_NS(600)
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#endif
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#endif
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#endif // HAS_SPI_LCD
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@ -0,0 +1,66 @@
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{
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"build": {
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"core": "stm32",
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"cpu": "cortex-m4",
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"extra_flags": "-DSTM32F407xx",
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"f_cpu": "168000000L",
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"hwids": [
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[
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"0x1EAF",
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"0x0003"
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],
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[
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"0x0483",
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"0x3748"
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]
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],
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"ldscript": "stm32f407xg.ld",
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"mcu": "stm32f407zgt6",
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"variant": "BIGTREE_GENERIC_STM32F407_5X"
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},
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"debug": {
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"jlink_device": "STM32F407ZG",
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"openocd_target": "stm32f4x",
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"svd_path": "STM32F40x.svd",
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"tools": {
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"stlink": {
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"server": {
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"arguments": [
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"-f",
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"scripts/interface/stlink.cfg",
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"-c",
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"transport select hla_swd",
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"-f",
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"scripts/target/stm32f4x.cfg",
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"-c",
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"reset_config none"
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],
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"executable": "bin/openocd",
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"package": "tool-openocd"
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}
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}
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}
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},
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"frameworks": [
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"arduino",
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"stm32cube"
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],
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"name": "STM32F407ZG (192k RAM. 1024k Flash)",
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"upload": {
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"disable_flushing": false,
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"maximum_ram_size": 196608,
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"maximum_size": 1048576,
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"protocol": "stlink",
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"protocols": [
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"stlink",
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"dfu",
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"jlink",
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"cmsis-dap"
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],
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"require_upload_port": true,
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"use_1200bps_touch": false,
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"wait_for_upload_port": false
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},
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"url": "http://www.st.com/en/microcontrollers/stm32f407zg.html",
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"vendor": "Generic"
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}
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@ -0,0 +1,29 @@
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import os,shutil
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from SCons.Script import DefaultEnvironment
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from platformio import util
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env = DefaultEnvironment()
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platform = env.PioPlatform()
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board = env.BoardConfig()
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FRAMEWORK_DIR = platform.get_package_dir("framework-arduinoststm32")
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CMSIS_DIR = os.path.join(FRAMEWORK_DIR, "CMSIS", "CMSIS")
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assert os.path.isdir(FRAMEWORK_DIR)
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assert os.path.isdir(CMSIS_DIR)
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assert os.path.isdir("buildroot/share/PlatformIO/variants")
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mcu_type = board.get("build.mcu")[:-2]
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variant = board.get("build.variant")
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series = mcu_type[:7].upper() + "xx"
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variant_dir = os.path.join(FRAMEWORK_DIR, "variants", variant)
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source_dir = os.path.join("buildroot/share/PlatformIO/variants", variant)
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assert os.path.isdir(source_dir)
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if not os.path.isdir(variant_dir):
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os.mkdir(variant_dir)
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for file_name in os.listdir(source_dir):
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full_file_name = os.path.join(source_dir, file_name)
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if os.path.isfile(full_file_name):
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shutil.copy(full_file_name, variant_dir)
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@ -0,0 +1,437 @@
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/*
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*******************************************************************************
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* Copyright (c) 2019, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* Automatically generated from STM32F407Z(E-G)Tx.xml
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*/
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#include "Arduino.h"
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#include "PeripheralPins.h"
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/* =====
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* Note: Commented lines are alternative possibilities which are not used by default.
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* If you change them, you should know what you're doing first.
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* =====
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*/
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//*** ADC ***
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#ifdef HAL_ADC_MODULE_ENABLED
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const PinMap PinMap_ADC[] = {
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{PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
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//{PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0
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//{PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0
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{PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
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//{PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
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|
//{PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
|
||||||
|
{PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
|
||||||
|
//{PA_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
|
||||||
|
//{PA_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
|
||||||
|
{PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
|
||||||
|
//{PA_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
|
||||||
|
//{PA_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
|
||||||
|
{PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
|
||||||
|
//{PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
|
||||||
|
{PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
|
||||||
|
//{PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
|
||||||
|
{PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
|
||||||
|
//{PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
|
||||||
|
{PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
|
||||||
|
//{PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
|
||||||
|
{PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
|
||||||
|
//{PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
|
||||||
|
{PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
|
||||||
|
//{PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
|
||||||
|
{PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
|
||||||
|
//{PC_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
|
||||||
|
//{PC_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
|
||||||
|
{PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
|
||||||
|
//{PC_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
|
||||||
|
//{PC_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
|
||||||
|
{PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
|
||||||
|
//{PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
|
||||||
|
//{PC_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
|
||||||
|
{PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
|
||||||
|
//{PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
|
||||||
|
//{PC_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
|
||||||
|
{PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
|
||||||
|
//{PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
|
||||||
|
{PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
|
||||||
|
//{PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
|
||||||
|
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio, 24 ADC
|
||||||
|
{PF_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
|
||||||
|
{PF_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
|
||||||
|
{PF_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15
|
||||||
|
{PF_6, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
|
||||||
|
{PF_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
|
||||||
|
{PF_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
|
||||||
|
{PF_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
|
||||||
|
{PF_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** DAC ***
|
||||||
|
|
||||||
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_DAC[] = {
|
||||||
|
{PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
|
||||||
|
{PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** I2C ***
|
||||||
|
|
||||||
|
#ifdef HAL_I2C_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_I2C_SDA[] = {
|
||||||
|
{PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||||
|
{PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||||
|
{PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||||
|
{PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_I2C_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_I2C_SCL[] = {
|
||||||
|
{PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
|
||||||
|
{PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||||
|
{PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||||
|
{PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** PWM ***
|
||||||
|
|
||||||
|
#ifdef HAL_TIM_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_PWM[] = {
|
||||||
|
{PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
|
||||||
|
//{PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
|
||||||
|
{PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
|
||||||
|
//{PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
|
||||||
|
{PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
|
||||||
|
//{PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
|
||||||
|
//{PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
|
||||||
|
{PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
|
||||||
|
//{PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
|
||||||
|
//{PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
|
||||||
|
{PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
|
||||||
|
//{PA_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
|
||||||
|
{PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||||
|
//{PA_6, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
|
||||||
|
//{PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
|
||||||
|
{PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
|
||||||
|
//{PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
|
||||||
|
//{PA_7, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
|
||||||
|
{PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
|
||||||
|
{PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
|
||||||
|
{PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
|
||||||
|
{PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
|
||||||
|
//{PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
|
||||||
|
//{PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
|
||||||
|
{PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
|
||||||
|
//{PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
|
||||||
|
//{PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
|
||||||
|
{PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
|
||||||
|
//{PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
|
||||||
|
//{PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
|
||||||
|
{PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||||
|
{PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
|
||||||
|
//{PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
|
||||||
|
//{PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
|
||||||
|
//{PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
|
||||||
|
{PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
|
||||||
|
//{PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
|
||||||
|
{PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
|
||||||
|
{PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
|
||||||
|
{PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
|
||||||
|
{PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
|
||||||
|
{PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
|
||||||
|
{PB_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
|
||||||
|
{PB_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
|
||||||
|
{PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
|
||||||
|
{PB_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
|
||||||
|
{PB_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
|
||||||
|
{PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||||
|
{PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
|
||||||
|
{PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
|
||||||
|
{PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
|
||||||
|
{PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
|
||||||
|
{PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
|
||||||
|
//{PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
|
||||||
|
//{PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
|
||||||
|
{PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
|
||||||
|
{PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
|
||||||
|
{PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
|
||||||
|
{PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
|
||||||
|
{PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
|
||||||
|
{PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
|
||||||
|
{PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
|
||||||
|
{PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
|
||||||
|
{PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
|
||||||
|
{PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
|
||||||
|
{PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
|
||||||
|
{PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
|
||||||
|
{PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PF_6, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
|
||||||
|
{PF_7, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
|
||||||
|
{PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
|
||||||
|
{PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** SERIAL ***
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_UART_TX[] = {
|
||||||
|
{PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||||
|
{PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
|
{PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
|
{PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
{PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
{PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||||
|
{PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
{PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||||
|
{PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_UART_RX[] = {
|
||||||
|
{PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||||
|
{PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
|
{PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
|
{PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
{PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
{PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||||
|
{PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
{PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||||
|
{PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_UART_RTS[] = {
|
||||||
|
{PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
|
{PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
{PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
{PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_UART_CTS[] = {
|
||||||
|
{PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
|
{PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
{PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||||
|
{PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
{PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** SPI ***
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_SPI_MOSI[] = {
|
||||||
|
{PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_SPI_MISO[] = {
|
||||||
|
{PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_SPI_SCLK[] = {
|
||||||
|
{PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_SPI_SSEL[] = {
|
||||||
|
{PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
|
||||||
|
{PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
|
||||||
|
{PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** CAN ***
|
||||||
|
|
||||||
|
#ifdef HAL_CAN_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_CAN_RD[] = {
|
||||||
|
{PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||||
|
{PB_5, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
|
||||||
|
{PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||||
|
{PB_12, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
|
||||||
|
{PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_CAN_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_CAN_TD[] = {
|
||||||
|
{PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||||
|
{PB_6, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
|
||||||
|
{PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||||
|
{PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
|
||||||
|
{PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** ETHERNET ***
|
||||||
|
|
||||||
|
#ifdef HAL_ETH_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_Ethernet[] = {
|
||||||
|
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
|
||||||
|
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK
|
||||||
|
{PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO
|
||||||
|
{PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL
|
||||||
|
{PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV
|
||||||
|
{PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2
|
||||||
|
{PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3
|
||||||
|
{PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
|
||||||
|
{PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
|
||||||
|
{PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER
|
||||||
|
{PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
|
||||||
|
{PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
|
||||||
|
{PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
|
||||||
|
{PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC
|
||||||
|
{PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2
|
||||||
|
{PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK
|
||||||
|
{PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0
|
||||||
|
{PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1
|
||||||
|
{PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
{PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
|
||||||
|
{PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
|
||||||
|
{PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
|
||||||
|
{PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
|
||||||
|
#endif
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** No QUADSPI ***
|
||||||
|
|
||||||
|
//*** USB ***
|
||||||
|
|
||||||
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_USB_OTG_FS[] = {
|
||||||
|
//{PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
|
||||||
|
//{PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
|
||||||
|
//{PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID
|
||||||
|
{PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM
|
||||||
|
{PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
|
const PinMap PinMap_USB_OTG_HS[] = {
|
||||||
|
#ifdef USE_USB_HS_IN_FS
|
||||||
|
{PA_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF
|
||||||
|
{PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID
|
||||||
|
{PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS
|
||||||
|
{PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM
|
||||||
|
{PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP
|
||||||
|
#else
|
||||||
|
{PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0
|
||||||
|
{PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK
|
||||||
|
{PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1
|
||||||
|
{PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2
|
||||||
|
{PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7
|
||||||
|
{PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3
|
||||||
|
{PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4
|
||||||
|
{PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5
|
||||||
|
{PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6
|
||||||
|
{PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP
|
||||||
|
{PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR
|
||||||
|
{PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT
|
||||||
|
#endif /* USE_USB_HS_IN_FS */
|
||||||
|
{NC, NP, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
@ -0,0 +1,50 @@
|
|||||||
|
/* SYS_WKUP */
|
||||||
|
#ifdef PWR_WAKEUP_PIN1
|
||||||
|
SYS_WKUP1 = PA_0,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN2
|
||||||
|
SYS_WKUP2 = NC,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN3
|
||||||
|
SYS_WKUP3 = NC,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN4
|
||||||
|
SYS_WKUP4 = NC,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN5
|
||||||
|
SYS_WKUP5 = NC,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN6
|
||||||
|
SYS_WKUP6 = NC,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN7
|
||||||
|
SYS_WKUP7 = NC,
|
||||||
|
#endif
|
||||||
|
#ifdef PWR_WAKEUP_PIN8
|
||||||
|
SYS_WKUP8 = NC,
|
||||||
|
#endif
|
||||||
|
/* USB */
|
||||||
|
#ifdef USBCON
|
||||||
|
USB_OTG_FS_SOF = PA_8,
|
||||||
|
USB_OTG_FS_VBUS = PA_9,
|
||||||
|
USB_OTG_FS_ID = PA_10,
|
||||||
|
USB_OTG_FS_DM = PA_11,
|
||||||
|
USB_OTG_FS_DP = PA_12,
|
||||||
|
USB_OTG_HS_ULPI_D0 = PA_3,
|
||||||
|
USB_OTG_HS_SOF = PA_4,
|
||||||
|
USB_OTG_HS_ULPI_CK = PA_5,
|
||||||
|
USB_OTG_HS_ULPI_D1 = PB_0,
|
||||||
|
USB_OTG_HS_ULPI_D2 = PB_1,
|
||||||
|
USB_OTG_HS_ULPI_D7 = PB_5,
|
||||||
|
USB_OTG_HS_ULPI_D3 = PB_10,
|
||||||
|
USB_OTG_HS_ULPI_D4 = PB_11,
|
||||||
|
USB_OTG_HS_ID = PB_12,
|
||||||
|
USB_OTG_HS_ULPI_D5 = PB_12,
|
||||||
|
USB_OTG_HS_ULPI_D6 = PB_13,
|
||||||
|
USB_OTG_HS_VBUS = PB_13,
|
||||||
|
USB_OTG_HS_DM = PB_14,
|
||||||
|
USB_OTG_HS_DP = PB_15,
|
||||||
|
USB_OTG_HS_ULPI_STP = PC_0,
|
||||||
|
USB_OTG_HS_ULPI_DIR = PC_2,
|
||||||
|
USB_OTG_HS_ULPI_NXT = PC_3,
|
||||||
|
#endif
|
||||||
@ -0,0 +1,208 @@
|
|||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F407ZGTx Device with
|
||||||
|
** 1024KByte FLASH, 128KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed as is, without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20020000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200;; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400;; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x8008000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text ALIGN(4):
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata ALIGN(4):
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
_siccmram = LOADADDR(.ccmram);
|
||||||
|
|
||||||
|
/* CCM-RAM section
|
||||||
|
*
|
||||||
|
* IMPORTANT NOTE!
|
||||||
|
* If initialized variables will be placed in this section,
|
||||||
|
* the startup code needs to be modified to copy the init-values.
|
||||||
|
*/
|
||||||
|
.ccmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sccmram = .; /* create a global symbol at ccmram start */
|
||||||
|
*(.ccmram)
|
||||||
|
*(.ccmram*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_eccmram = .; /* create a global symbol at ccmram end */
|
||||||
|
} >CCMRAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,481 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f4xx_hal_conf.h
|
||||||
|
* @brief HAL configuration file.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F4xx_HAL_CONF_H
|
||||||
|
#define __STM32F4xx_HAL_CONF_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* ########################## Module Selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief This is the list of modules to be used in the HAL driver
|
||||||
|
*/
|
||||||
|
#define HAL_MODULE_ENABLED
|
||||||
|
#define HAL_ADC_MODULE_ENABLED
|
||||||
|
/* #define HAL_CAN_MODULE_ENABLED */
|
||||||
|
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||||
|
#define HAL_CRC_MODULE_ENABLED
|
||||||
|
/* #define HAL_CEC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||||
|
#define HAL_DAC_MODULE_ENABLED
|
||||||
|
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||||
|
#define HAL_DMA_MODULE_ENABLED
|
||||||
|
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||||
|
/* #define HAL_ETH_MODULE_ENABLED */
|
||||||
|
#define HAL_FLASH_MODULE_ENABLED
|
||||||
|
/* #define HAL_NAND_MODULE_ENABLED */
|
||||||
|
/* #define HAL_NOR_MODULE_ENABLED */
|
||||||
|
/* #define HAL_PCCARD_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||||
|
/* #define HAL_HASH_MODULE_ENABLED */
|
||||||
|
#define HAL_GPIO_MODULE_ENABLED
|
||||||
|
/* #define HAL_EXTI_MODULE_ENABLED */
|
||||||
|
#define HAL_I2C_MODULE_ENABLED
|
||||||
|
/* #define HAL_SMBUS_MODULE_ENABLED */
|
||||||
|
/* #define HAL_I2S_MODULE_ENABLED */
|
||||||
|
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||||
|
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_DSI_MODULE_ENABLED */
|
||||||
|
#define HAL_PWR_MODULE_ENABLED
|
||||||
|
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||||
|
#define HAL_RCC_MODULE_ENABLED
|
||||||
|
/* #define HAL_RNG_MODULE_ENABLED */
|
||||||
|
#define HAL_RTC_MODULE_ENABLED
|
||||||
|
/* #define HAL_SAI_MODULE_ENABLED */
|
||||||
|
#define HAL_SD_MODULE_ENABLED
|
||||||
|
#define HAL_SPI_MODULE_ENABLED
|
||||||
|
#define HAL_TIM_MODULE_ENABLED
|
||||||
|
/* #define HAL_UART_MODULE_ENABLED */
|
||||||
|
/* #define HAL_USART_MODULE_ENABLED */
|
||||||
|
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
|
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||||
|
#define HAL_CORTEX_MODULE_ENABLED
|
||||||
|
#define HAL_PCD_MODULE_ENABLED
|
||||||
|
/* #define HAL_HCD_MODULE_ENABLED */
|
||||||
|
/* #define HAL_FMPI2C_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||||
|
/* #define HAL_DFSDM_MODULE_ENABLED */
|
||||||
|
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||||
|
/* #define HAL_MMC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||||
|
/**
|
||||||
|
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||||
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
|
* (when HSE is used as system clock source, directly or through the PLL).
|
||||||
|
*/
|
||||||
|
#if !defined (HSE_VALUE)
|
||||||
|
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||||
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||||
|
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
|
||||||
|
#endif /* HSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Internal High Speed oscillator (HSI) value.
|
||||||
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
|
* (when HSI is used as system clock source, directly or through the PLL).
|
||||||
|
*/
|
||||||
|
#if !defined (HSI_VALUE)
|
||||||
|
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
|
||||||
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Internal Low Speed oscillator (LSI) value.
|
||||||
|
*/
|
||||||
|
#if !defined (LSI_VALUE)
|
||||||
|
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
|
||||||
|
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||||
|
The real value may vary depending on the variations
|
||||||
|
in voltage and temperature.*/
|
||||||
|
/**
|
||||||
|
* @brief External Low Speed oscillator (LSE) value.
|
||||||
|
*/
|
||||||
|
#if !defined (LSE_VALUE)
|
||||||
|
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
|
||||||
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||||
|
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
|
||||||
|
#endif /* LSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief External clock source for I2S peripheral
|
||||||
|
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||||
|
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||||
|
*/
|
||||||
|
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||||
|
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
|
||||||
|
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||||
|
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||||
|
|
||||||
|
/* ########################### System Configuration ######################### */
|
||||||
|
/**
|
||||||
|
* @brief This is the HAL system configuration section
|
||||||
|
*/
|
||||||
|
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
|
||||||
|
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
|
||||||
|
#define USE_RTOS 0U
|
||||||
|
#define PREFETCH_ENABLE 1U
|
||||||
|
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||||
|
#define DATA_CACHE_ENABLE 1U
|
||||||
|
|
||||||
|
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||||
|
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||||
|
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||||
|
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||||
|
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||||
|
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||||
|
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||||
|
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||||
|
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||||
|
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||||
|
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||||
|
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||||
|
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||||
|
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
|
||||||
|
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||||
|
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||||
|
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||||
|
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||||
|
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||||
|
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||||
|
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||||
|
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
|
||||||
|
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||||
|
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||||
|
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||||
|
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||||
|
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||||
|
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||||
|
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||||
|
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||||
|
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||||
|
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||||
|
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||||
|
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||||
|
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||||
|
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||||
|
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||||
|
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||||
|
|
||||||
|
/* ########################## Assert Selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||||
|
* HAL drivers code
|
||||||
|
*/
|
||||||
|
/* #define USE_FULL_ASSERT 1U */
|
||||||
|
|
||||||
|
/* ################## Ethernet peripheral configuration ##################### */
|
||||||
|
|
||||||
|
/* Section 1 : Ethernet peripheral configuration */
|
||||||
|
|
||||||
|
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||||
|
#define MAC_ADDR0 2U
|
||||||
|
#define MAC_ADDR1 0U
|
||||||
|
#define MAC_ADDR2 0U
|
||||||
|
#define MAC_ADDR3 0U
|
||||||
|
#define MAC_ADDR4 0U
|
||||||
|
#define MAC_ADDR5 0U
|
||||||
|
|
||||||
|
/* Definition of the Ethernet driver buffers size and count */
|
||||||
|
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||||
|
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||||
|
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||||
|
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||||
|
|
||||||
|
/* Section 2: PHY configuration section */
|
||||||
|
|
||||||
|
/* DP83848_PHY_ADDRESS Address*/
|
||||||
|
#define DP83848_PHY_ADDRESS 0x01U
|
||||||
|
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||||
|
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
|
||||||
|
/* PHY Configuration delay */
|
||||||
|
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
|
||||||
|
|
||||||
|
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
|
||||||
|
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
|
||||||
|
|
||||||
|
/* Section 3: Common PHY Registers */
|
||||||
|
|
||||||
|
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
|
||||||
|
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
|
||||||
|
|
||||||
|
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
|
||||||
|
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
|
||||||
|
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||||
|
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||||
|
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||||
|
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||||
|
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
|
||||||
|
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
|
||||||
|
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
|
||||||
|
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
|
||||||
|
|
||||||
|
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
|
||||||
|
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
|
||||||
|
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
|
||||||
|
|
||||||
|
/* Section 4: Extended PHY Registers */
|
||||||
|
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
|
||||||
|
|
||||||
|
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||||
|
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||||
|
|
||||||
|
/* ################## SPI peripheral configuration ########################## */
|
||||||
|
|
||||||
|
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||||
|
* Activated: CRC code is present inside driver
|
||||||
|
* Deactivated: CRC code cleaned from driver
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USE_SPI_CRC 0U
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @brief Include module's header file
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_RCC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_rcc.h"
|
||||||
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_gpio.h"
|
||||||
|
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_exti.h"
|
||||||
|
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DMA_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_dma.h"
|
||||||
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_cortex.h"
|
||||||
|
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_ADC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_adc.h"
|
||||||
|
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CAN_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_can.h"
|
||||||
|
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_can_legacy.h"
|
||||||
|
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CRC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_crc.h"
|
||||||
|
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_cryp.h"
|
||||||
|
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_dma2d.h"
|
||||||
|
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_dac.h"
|
||||||
|
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_dcmi.h"
|
||||||
|
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_ETH_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_eth.h"
|
||||||
|
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_flash.h"
|
||||||
|
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_sram.h"
|
||||||
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_NOR_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_nor.h"
|
||||||
|
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_NAND_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_nand.h"
|
||||||
|
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_pccard.h"
|
||||||
|
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_sdram.h"
|
||||||
|
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_HASH_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_hash.h"
|
||||||
|
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_I2C_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_i2c.h"
|
||||||
|
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_smbus.h"
|
||||||
|
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_I2S_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_i2s.h"
|
||||||
|
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_iwdg.h"
|
||||||
|
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_ltdc.h"
|
||||||
|
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PWR_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_pwr.h"
|
||||||
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_RNG_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_rng.h"
|
||||||
|
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_RTC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_rtc.h"
|
||||||
|
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SAI_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_sai.h"
|
||||||
|
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SD_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_sd.h"
|
||||||
|
#endif /* HAL_SD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_spi.h"
|
||||||
|
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_TIM_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_tim.h"
|
||||||
|
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_uart.h"
|
||||||
|
#endif /* HAL_UART_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_USART_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_usart.h"
|
||||||
|
#endif /* HAL_USART_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_irda.h"
|
||||||
|
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_smartcard.h"
|
||||||
|
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_wwdg.h"
|
||||||
|
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_pcd.h"
|
||||||
|
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_HCD_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_hcd.h"
|
||||||
|
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DSI_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_dsi.h"
|
||||||
|
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_qspi.h"
|
||||||
|
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CEC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_cec.h"
|
||||||
|
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_FMPI2C_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_fmpi2c.h"
|
||||||
|
#endif /* HAL_FMPI2C_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_spdifrx.h"
|
||||||
|
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_dfsdm.h"
|
||||||
|
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_lptim.h"
|
||||||
|
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_MMC_MODULE_ENABLED
|
||||||
|
#include "stm32f4xx_hal_mmc.h"
|
||||||
|
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
/**
|
||||||
|
* @brief The assert_param macro is used for function's parameters check.
|
||||||
|
* @param expr: If expr is false, it calls assert_failed function
|
||||||
|
* which reports the name of the source file and the source
|
||||||
|
* line number of the call that failed.
|
||||||
|
* If expr is true, it returns no value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||||
|
/* Exported functions ------------------------------------------------------- */
|
||||||
|
void assert_failed(uint8_t *file, uint32_t line);
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F4xx_HAL_CONF_H */
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,287 @@
|
|||||||
|
/*
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2017, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "variant.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Pin number
|
||||||
|
// This array allows to wrap Arduino pin number(Dx or x)
|
||||||
|
// to STM32 PinName (PX_n)
|
||||||
|
const PinName digitalPin[] = {
|
||||||
|
#if STM32F4X_PIN_NUM >= 64 //64 pins mcu, 51 gpio
|
||||||
|
PC_13, //D0
|
||||||
|
PC_14, //D1 - OSC32_IN
|
||||||
|
PC_15, //D2 - OSC32_OUT
|
||||||
|
PH_0, //D3 - OSC_IN
|
||||||
|
PH_1, //D4 - OSC_OUT
|
||||||
|
PC_0, //D5 - 1: 2:ADC123_IN10
|
||||||
|
PC_1, //D6 - 1: 2:ADC123_IN11
|
||||||
|
PC_2, //D7 - 1:SPI2_MISO 2:ADC123_IN12
|
||||||
|
PC_3, //D8 - 1:SPI2_MOSI 2:ADC123_IN13
|
||||||
|
PA_0, //D9 - 1:UART4_TX / TIM5_CH1 2:ADC123_IN0
|
||||||
|
PA_1, //D10 - 1:UART4_RX / TIM5_CH2 / TIM2_CH2 2:ADC123_IN1
|
||||||
|
PA_2, //D11 - 1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3 2:ADC123_IN2
|
||||||
|
PA_3, //D12 - 1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4 2:ADC123_IN3
|
||||||
|
PA_4, //D13 - NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK 2:ADC12_IN4 / DAC_OUT1
|
||||||
|
PA_5, //D14 - NOT FT 1:SPI1_SCK 2:ADC12_IN5 / DAC_OUT2
|
||||||
|
PA_6, //D15 - 1:SPI1_MISO / TIM13_CH1 / TIM3_CH1 2:ADC12_IN6
|
||||||
|
PA_7, //D16 - 1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2 2:ADC12_IN7
|
||||||
|
PC_4, //D17 - 1: 2:ADC12_IN14
|
||||||
|
PC_5, //D18 - 1: 2:ADC12_IN15
|
||||||
|
PB_0, //D19 - 1:TIM3_CH3 2:ADC12_IN8
|
||||||
|
PB_1, //D20 - 1:TIM3_CH4 2:ADC12_IN9
|
||||||
|
PB_2, //D21 - BOOT1
|
||||||
|
PB_10, //D22 - 1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
|
||||||
|
PB_11, //D23 - 1:I2C2_SDA / USART3_RX / TIM2_CH4
|
||||||
|
PB_12, //D24 - 1:SPI2_NSS / OTG_HS_ID
|
||||||
|
PB_13, //D25 - 1:SPI2_SCK 2:OTG_HS_VBUS
|
||||||
|
PB_14, //D26 - 1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
|
||||||
|
PB_15, //D27 - SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
|
||||||
|
PC_6, //D28 - 1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
|
||||||
|
PC_7, //D29 - 1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
|
||||||
|
PC_8, //D30 - 1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
|
||||||
|
PC_9, //D31 - 1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
|
||||||
|
PA_8, //D32 - 1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
|
||||||
|
PA_9, //D33 - 1:USART1_TX / TIM1_CH2 2:OTG_FS_VBUS
|
||||||
|
PA_10, //34 - 1:USART1_RX / TIM1_CH3 / OTG_FS_ID
|
||||||
|
PA_11, //D35 - 1:TIM1_CH4 / OTG_FS_DM
|
||||||
|
PA_12, //D36 - 1:OTG_FS_DP
|
||||||
|
PA_13, //D37 - 0:JTMS-SWDIO
|
||||||
|
PA_14, //D38 - 0:JTCK-SWCLK
|
||||||
|
PA_15, //D39 - 0:JTDI 1:SPI3_NSS / SPI1_NSS
|
||||||
|
PC_10, //D40 - 1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
|
||||||
|
PC_11, //D41 - 1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
|
||||||
|
PC_12, //D42 - 1:UART5_TX / SPI3_MOSI / SDIO_CK
|
||||||
|
PD_2, //D43 - 1:UART5_RX / SDIO_CMD
|
||||||
|
PB_3, //D44 - 0:JTDO 1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
|
||||||
|
PB_4, //D45 - 0:NJTRST 1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
|
||||||
|
PB_5, //D45 - 1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
|
||||||
|
PB_6, //D47 - 1:I2C1_SCL / TIM4_CH1 / USART1_TX
|
||||||
|
PB_7, //D48 - 1:I2C1_SDA / TIM4_CH2 / USART1_RX
|
||||||
|
PB_8, //D49 - 1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
|
||||||
|
PB_9, //D50 - 1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 100 //100 pins mcu, 82 gpio
|
||||||
|
PE_2, //D51 - 1:FSMC_A23
|
||||||
|
PE_3, //D52 - 1:FSMC_A19
|
||||||
|
PE_4, //D53 - 1:FSMC_A20
|
||||||
|
PE_5, //D54 - 1:FSMC_A21
|
||||||
|
PE_6, //D55 - 1:FSMC_A22
|
||||||
|
PE_7, //D56 - 1:FSMC_D4
|
||||||
|
PE_8, //D57 - 1:FSMC_D5
|
||||||
|
PE_9, //D58 - 1:FSMC_D6 / TIM1_CH1
|
||||||
|
PE_10, //D59 - 1:FSMC_D7
|
||||||
|
PE_11, //D60 - 1:FSMC_D8 / TIM1_CH2
|
||||||
|
PE_12, //D61 - 1:FSMC_D9
|
||||||
|
PE_13, //D62 - 1:FSMC_D10 / TIM1_CH3
|
||||||
|
PE_14, //D63 - 1:FSMC_D11 / TIM1_CH4
|
||||||
|
PE_15, //D64 - 1:FSMC_D12
|
||||||
|
PD_8, //D65 - 1:FSMC_D13 / USART3_TX
|
||||||
|
PD_9, //D66 - 1:FSMC_D14 / USART3_RX
|
||||||
|
PD_10, //D67 - 1:FSMC_D15
|
||||||
|
PD_11, //D68 - 1:FSMC_A16
|
||||||
|
PD_12, //D69 - 1:FSMC_A17 / TIM4_CH1
|
||||||
|
PD_13, //D70 - 1:FSMC_A18 / TIM4_CH2
|
||||||
|
PD_14, //D71 - 1:FSMC_D0 / TIM4_CH3
|
||||||
|
PD_15, //D72 - 1:FSMC_D1 / TIM4_CH4
|
||||||
|
PD_0, //D73 - 1:FSMC_D2
|
||||||
|
PD_1, //D74 - 1:FSMC_D3
|
||||||
|
PD_3, //D75 - 1:FSMC_CLK
|
||||||
|
PD_4, //D76 - 1:FSMC_NOE
|
||||||
|
PD_5, //D77 - 1:USART2_TX
|
||||||
|
PD_6, //D78 - 1:USART2_RX
|
||||||
|
PD_7, //D79
|
||||||
|
PE_0, //D80
|
||||||
|
PE_1, //D81
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
PF_0, //D82 - 1:FSMC_A0 / I2C2_SDA
|
||||||
|
PF_1, //D83 - 1:FSMC_A1 / I2C2_SCL
|
||||||
|
PF_2, //D84 - 1:FSMC_A2
|
||||||
|
PF_3, //D85 - 1:FSMC_A3 2:ADC3_IN9
|
||||||
|
PF_4, //D86 - 1:FSMC_A4 2:ADC3_IN14
|
||||||
|
PF_5, //D87 - 1:FSMC_A5 2:ADC3_IN15
|
||||||
|
PF_6, //D88 - 1:TIM10_CH1 2:ADC3_IN4
|
||||||
|
PF_7, //D89 - 1:TIM11_CH1 2:ADC3_IN5
|
||||||
|
PF_8, //D90 - 1:TIM13_CH1 2:ADC3_IN6
|
||||||
|
PF_9, //D91 - 1;TIM14_CH1 2:ADC3_IN7
|
||||||
|
PF_10, //D92 - 2:ADC3_IN8
|
||||||
|
PF_11, //D93
|
||||||
|
PF_12, //D94 - 1:FSMC_A6
|
||||||
|
PF_13, //D95 - 1:FSMC_A7
|
||||||
|
PF_14, //D96 - 1:FSMC_A8
|
||||||
|
PF_15, //D97 - 1:FSMC_A9
|
||||||
|
PG_0, //D98 - 1:FSMC_A10
|
||||||
|
PG_1, //D99 - 1:FSMC_A11
|
||||||
|
PG_2, //D100 - 1:FSMC_A12
|
||||||
|
PG_3, //D101 - 1:FSMC_A13
|
||||||
|
PG_4, //D102 - 1:FSMC_A14
|
||||||
|
PG_5, //D103 - 1:FSMC_A15
|
||||||
|
PG_6, //D104
|
||||||
|
PG_7, //D105
|
||||||
|
PG_8, //D106
|
||||||
|
PG_9, //D107 - 1:USART6_RX
|
||||||
|
PG_10, //D108 - 1:FSMC_NE3
|
||||||
|
PG_11, //D109
|
||||||
|
PG_12, //D110 - 1:FSMC_NE4
|
||||||
|
PG_13, //D111 - 1:FSMC_A24
|
||||||
|
PG_14, //D112 - 1:FSMC_A25 / USART6_TX
|
||||||
|
PG_15, //D113
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 176 //176 pins mcu, 140 gpio
|
||||||
|
PI_8, //D114
|
||||||
|
PI_9, //D115
|
||||||
|
PI_10, //D116
|
||||||
|
PI_11, //D117
|
||||||
|
PH_2, //D118
|
||||||
|
PH_3, //D119
|
||||||
|
PH_4, //D120 - 1:I2C2_SCL
|
||||||
|
PH_5, //D121 - 1:I2C2_SDA
|
||||||
|
PH_6, //D122 - 1:TIM12_CH1
|
||||||
|
PH_7, //D123 - 1:I2C3_SCL
|
||||||
|
PH_8, //D124 - 1:I2C3_SDA
|
||||||
|
PH_9, //D125 - 1:TIM12_CH2
|
||||||
|
PH_10, //D126 - 1:TIM5_CH1
|
||||||
|
PH_11, //D127 - 1:TIM5_CH2
|
||||||
|
PH_12, //D128 - 1:TIM5_CH3
|
||||||
|
PH_13, //D129
|
||||||
|
PH_14, //D130
|
||||||
|
PH_15, //D131
|
||||||
|
PI_0, //D132 - 1:TIM5_CH4 / SPI2_NSS
|
||||||
|
PI_1, //D133 - 1:SPI2_SCK
|
||||||
|
PI_2, //D134 - 1:TIM8_CH4 /SPI2_MISO
|
||||||
|
PI_3, //D135 - 1:SPI2_MOS
|
||||||
|
PI_4, //D136
|
||||||
|
PI_5, //D137 - 1:TIM8_CH1
|
||||||
|
PI_6, //D138 - 1:TIM8_CH2
|
||||||
|
PI_7, //D139 - 1:TIM8_CH3
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 64 //64 pins mcu, 51 gpio, 16 ADC
|
||||||
|
PA_0, //D140/A0 = D9 - 1:UART4_TX / TIM5_CH1 2:ADC123_IN0
|
||||||
|
PA_1, //D141/A1 = D10 - 1:UART4_RX / TIM5_CH2 / TIM2_CH2 2:ADC123_IN1
|
||||||
|
PA_2, //D142/A2 = D11 - 1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3 2:ADC123_IN2
|
||||||
|
PA_3, //D143/A3 = D12 - 1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4 2:ADC123_IN3
|
||||||
|
PA_4, //D144/A4 = D13 - NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK 2:ADC12_IN4 / DAC_OUT1
|
||||||
|
PA_5, //D145/A5 = D14 - NOT FT 1:SPI1_SCK 2:ADC12_IN5 / DAC_OUT2
|
||||||
|
PA_6, //D146/A6 = D15 - 1:SPI1_MISO / TIM13_CH1 / TIM3_CH1 2:ADC12_IN6
|
||||||
|
PA_7, //D147/A7 = D16 - 1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2 2:ADC12_IN7
|
||||||
|
PB_0, //D148/A8 = D19 - 1:TIM3_CH3 2:ADC12_IN8
|
||||||
|
PB_1, //D149/A9 = D20 - 1:TIM3_CH4 2:ADC12_IN9
|
||||||
|
PC_0, //D150/A10 = D5 - 1: 2:ADC123_IN10
|
||||||
|
PC_1, //D151/A11 = D6 - 1: 2:ADC123_IN11
|
||||||
|
PC_2, //D152/A12 = D7 - 1:SPI2_MISO 2:ADC123_IN12
|
||||||
|
PC_3, //D153/A13 = D8 - 1:SPI2_MOSI 2:ADC123_IN13
|
||||||
|
PC_4, //D154/A14 = D17 - 1: 2:ADC12_IN14
|
||||||
|
PC_5, //D155/A15 = D18 - 1: 2:ADC12_IN15
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio, 24 ADC
|
||||||
|
PF_3, //D156/A16 = D85 - 1:FSMC_A3 2:ADC3_IN9
|
||||||
|
PF_4, //D157/A17 = D86 - 1:FSMC_A4 2:ADC3_IN14
|
||||||
|
PF_5, //D158/A18 = D87 - 1:FSMC_A5 2:ADC3_IN15
|
||||||
|
PF_6, //D159/A19 = D88 - 1:TIM10_CH1 2:ADC3_IN4
|
||||||
|
PF_7, //D160/A20 = D89 - 1:TIM11_CH1 2:ADC3_IN5
|
||||||
|
PF_8, //D161/A21 = D90 - 1:TIM13_CH1 2:ADC3_IN6
|
||||||
|
PF_9, //D162/A22 = D91 - 1;TIM14_CH1 2:ADC3_IN7
|
||||||
|
PF_10, //D163/A23 = D92 - 2:ADC3_IN8
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// ----------------------------------------------------------------------------
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System Clock Configuration
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
WEAK void SystemClock_Config(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||||
|
|
||||||
|
/**Configure the main internal regulator output voltage
|
||||||
|
*/
|
||||||
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||||||
|
|
||||||
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||||
|
|
||||||
|
/**Initializes the CPU, AHB and APB busses clocks
|
||||||
|
*/
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||||
|
RCC_OscInitStruct.PLL.PLLM = 8;
|
||||||
|
RCC_OscInitStruct.PLL.PLLN = 336;
|
||||||
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||||
|
RCC_OscInitStruct.PLL.PLLQ = 7;
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
|
_Error_Handler(__FILE__, __LINE__);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**Initializes the CPU, AHB and APB busses clocks
|
||||||
|
*/
|
||||||
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
|
||||||
|
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||||
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||||
|
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
|
||||||
|
_Error_Handler(__FILE__, __LINE__);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**Configure the Systick interrupt time
|
||||||
|
*/
|
||||||
|
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
|
||||||
|
|
||||||
|
/**Configure the Systick
|
||||||
|
*/
|
||||||
|
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
|
||||||
|
|
||||||
|
/* SysTick_IRQn interrupt configuration */
|
||||||
|
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
@ -0,0 +1,296 @@
|
|||||||
|
/*
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2017, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _VARIANT_ARDUINO_STM32_
|
||||||
|
#define _VARIANT_ARDUINO_STM32_
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
* Headers
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
#include "PeripheralPins.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif // __cplusplus
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
* Pins
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
extern const PinName digitalPin[];
|
||||||
|
|
||||||
|
#ifdef STM32F405RX
|
||||||
|
#define STM32F4X_PIN_NUM 64 //64 pins mcu, 51 gpio
|
||||||
|
#define STM32F4X_GPIO_NUM 51
|
||||||
|
#define STM32F4X_ADC_NUM 16
|
||||||
|
#elif defined STM32F407_5VX
|
||||||
|
#define STM32F4X_PIN_NUM 100 //100 pins mcu, 82 gpio
|
||||||
|
#define STM32F4X_GPIO_NUM 82
|
||||||
|
#define STM32F4X_ADC_NUM 16
|
||||||
|
#elif defined STM32F407_5ZX
|
||||||
|
#define STM32F4X_PIN_NUM 144 //144 pins mcu, 114 gpio
|
||||||
|
#define STM32F4X_GPIO_NUM 114
|
||||||
|
#define STM32F4X_ADC_NUM 24
|
||||||
|
#elif defined STM32F407IX
|
||||||
|
#define STM32F4X_PIN_NUM 176 //176 pins mcu, 140 gpio
|
||||||
|
#define STM32F4X_GPIO_NUM 140
|
||||||
|
#define STM32F4X_ADC_NUM 24
|
||||||
|
#else
|
||||||
|
#error "no match MCU defined"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32F4X_PIN_NUM >= 64 //64 pins mcu, 51 gpio
|
||||||
|
#define PC13 0
|
||||||
|
#define PC14 1 //OSC32_IN
|
||||||
|
#define PC15 2 //OSC32_OUT
|
||||||
|
#define PH0 3 //OSC_IN
|
||||||
|
#define PH1 4 //OSC_OUT
|
||||||
|
#define PC0 5 //1: 2:ADC123_IN10
|
||||||
|
#define PC1 6 //1: 2:ADC123_IN11
|
||||||
|
#define PC2 7 //1:SPI2_MISO 2:ADC123_IN12
|
||||||
|
#define PC3 8 //1:SPI2_MOSI 2:ADC123_IN13
|
||||||
|
#define PA0 9 //1:UART4_TX / TIM5_CH1 2:ADC123_IN0
|
||||||
|
#define PA1 10 //1:UART4_RX / TIM5_CH2 / TIM2_CH2 2:ADC123_IN1
|
||||||
|
#define PA2 11 //1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3 2:ADC123_IN2
|
||||||
|
#define PA3 12 //1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4 2:ADC123_IN3
|
||||||
|
#define PA4 13 //NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK 2:ADC12_IN4 / DAC_OUT1
|
||||||
|
#define PA5 14 //NOT FT 1:SPI1_SCK 2:ADC12_IN5 / DAC_OUT2
|
||||||
|
#define PA6 15 //1:SPI1_MISO / TIM13_CH1 / TIM3_CH1 2:ADC12_IN6
|
||||||
|
#define PA7 16 //1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2 2:ADC12_IN7
|
||||||
|
#define PC4 17 //1: 2:ADC12_IN14
|
||||||
|
#define PC5 18 //1: 2:ADC12_IN15
|
||||||
|
#define PB0 19 //1:TIM3_CH3 2:ADC12_IN8
|
||||||
|
#define PB1 20 //1:TIM3_CH4 2:ADC12_IN9
|
||||||
|
#define PB2 21 //BOOT1
|
||||||
|
#define PB10 22 //1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
|
||||||
|
#define PB11 23 //1:I2C2_SDA / USART3_RX / TIM2_CH4
|
||||||
|
#define PB12 24 //1:SPI2_NSS / OTG_HS_ID
|
||||||
|
#define PB13 25 //1:SPI2_SCK 2:OTG_HS_VBUS
|
||||||
|
#define PB14 26 //1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
|
||||||
|
#define PB15 27 //SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
|
||||||
|
#define PC6 28 //1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
|
||||||
|
#define PC7 29 //1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
|
||||||
|
#define PC8 30 //1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
|
||||||
|
#define PC9 31 //1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
|
||||||
|
#define PA8 32 //1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
|
||||||
|
#define PA9 33 //1:USART1_TX / TIM1_CH2 2:OTG_FS_VBUS
|
||||||
|
#define PA10 34 //1:USART1_RX / TIM1_CH3 / OTG_FS_ID
|
||||||
|
#define PA11 35 //1:TIM1_CH4 / OTG_FS_DM
|
||||||
|
#define PA12 36 //1:OTG_FS_DP
|
||||||
|
#define PA13 37 //0:JTMS-SWDIO
|
||||||
|
#define PA14 38 //0:JTCK-SWCLK
|
||||||
|
#define PA15 39 //0:JTDI 1:SPI3_NSS / SPI1_NSS
|
||||||
|
#define PC10 40 //1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
|
||||||
|
#define PC11 41 //1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
|
||||||
|
#define PC12 42 //1:UART5_TX / SPI3_MOSI / SDIO_CK
|
||||||
|
#define PD2 43 //1:UART5_RX / SDIO_CMD
|
||||||
|
#define PB3 44 //0:JTDO 1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
|
||||||
|
#define PB4 45 //0:NJTRST 1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
|
||||||
|
#define PB5 45 //1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
|
||||||
|
#define PB6 47 //1:I2C1_SCL / TIM4_CH1 / USART1_TX
|
||||||
|
#define PB7 48 //1:I2C1_SDA / TIM4_CH2 / USART1_RX
|
||||||
|
#define PB8 49 //1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
|
||||||
|
#define PB9 50 //1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 100 //100 pins mcu, 82 gpio
|
||||||
|
#define PE2 51 //1:FSMC_A23
|
||||||
|
#define PE3 52 //1:FSMC_A19
|
||||||
|
#define PE4 53 //1:FSMC_A20
|
||||||
|
#define PE5 54 //1:FSMC_A21
|
||||||
|
#define PE6 55 //1:FSMC_A22
|
||||||
|
#define PE7 56 //1:FSMC_D4
|
||||||
|
#define PE8 57 //1:FSMC_D5
|
||||||
|
#define PE9 58 //1:FSMC_D6 / TIM1_CH1
|
||||||
|
#define PE10 59 //1:FSMC_D7
|
||||||
|
#define PE11 60 //1:FSMC_D8 / TIM1_CH2
|
||||||
|
#define PE12 61 //1:FSMC_D9
|
||||||
|
#define PE13 62 //1:FSMC_D10 / TIM1_CH3
|
||||||
|
#define PE14 63 //1:FSMC_D11 / TIM1_CH4
|
||||||
|
#define PE15 64 //1:FSMC_D12
|
||||||
|
#define PD8 65 //1:FSMC_D13 / USART3_TX
|
||||||
|
#define PD9 66 //1:FSMC_D14 / USART3_RX
|
||||||
|
#define PD10 67 //1:FSMC_D15
|
||||||
|
#define PD11 68 //1:FSMC_A16
|
||||||
|
#define PD12 69 //1:FSMC_A17 / TIM4_CH1
|
||||||
|
#define PD13 70 //1:FSMC_A18 / TIM4_CH2
|
||||||
|
#define PD14 71 //1:FSMC_D0 / TIM4_CH3
|
||||||
|
#define PD15 72 //1:FSMC_D1 / TIM4_CH4
|
||||||
|
#define PD0 73 //1:FSMC_D2
|
||||||
|
#define PD1 74 //1:FSMC_D3
|
||||||
|
#define PD3 75 //1:FSMC_CLK
|
||||||
|
#define PD4 76 //1:FSMC_NOE
|
||||||
|
#define PD5 77 //1:USART2_TX
|
||||||
|
#define PD6 78 //1:USART2_RX
|
||||||
|
#define PD7 79
|
||||||
|
#define PE0 80
|
||||||
|
#define PE1 81
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
|
||||||
|
#define PF0 82 //1:FSMC_A0 / I2C2_SDA
|
||||||
|
#define PF1 83 //1:FSMC_A1 / I2C2_SCL
|
||||||
|
#define PF2 84 //1:FSMC_A2
|
||||||
|
#define PF3 85 //1:FSMC_A3 2:ADC3_IN9
|
||||||
|
#define PF4 86 //1:FSMC_A4 2:ADC3_IN14
|
||||||
|
#define PF5 87 //1:FSMC_A5 2:ADC3_IN15
|
||||||
|
#define PF6 88 //1:TIM10_CH1 2:ADC3_IN4
|
||||||
|
#define PF7 89 //1:TIM11_CH1 2:ADC3_IN5
|
||||||
|
#define PF8 90 //1:TIM13_CH1 2:ADC3_IN6
|
||||||
|
#define PF9 91 //1;TIM14_CH1 2:ADC3_IN7
|
||||||
|
#define PF10 92 //2:ADC3_IN8
|
||||||
|
#define PF11 93
|
||||||
|
#define PF12 94 //1:FSMC_A6
|
||||||
|
#define PF13 95 //1:FSMC_A7
|
||||||
|
#define PF14 96 //1:FSMC_A8
|
||||||
|
#define PF15 97 //1:FSMC_A9
|
||||||
|
#define PG0 98 //1:FSMC_A10
|
||||||
|
#define PG1 99 //1:FSMC_A11
|
||||||
|
#define PG2 100 //1:FSMC_A12
|
||||||
|
#define PG3 101 //1:FSMC_A13
|
||||||
|
#define PG4 102 //1:FSMC_A14
|
||||||
|
#define PG5 103 //1:FSMC_A15
|
||||||
|
#define PG6 104
|
||||||
|
#define PG7 105
|
||||||
|
#define PG8 106
|
||||||
|
#define PG9 107 //1:USART6_RX
|
||||||
|
#define PG10 108 //1:FSMC_NE3
|
||||||
|
#define PG11 109
|
||||||
|
#define PG12 110 //1:FSMC_NE4
|
||||||
|
#define PG13 111 //1:FSMC_A24
|
||||||
|
#define PG14 112 //1:FSMC_A25 / USART6_TX
|
||||||
|
#define PG15 113
|
||||||
|
#endif
|
||||||
|
#if STM32F4X_PIN_NUM >= 176 //176 pins mcu, 140 gpio
|
||||||
|
#define PI8 114
|
||||||
|
#define PI9 115
|
||||||
|
#define PI10 116
|
||||||
|
#define PI11 117
|
||||||
|
#define PH2 118
|
||||||
|
#define PH3 119
|
||||||
|
#define PH4 120 //1:I2C2_SCL
|
||||||
|
#define PH5 121 //1:I2C2_SDA
|
||||||
|
#define PH6 122 //1:TIM12_CH1
|
||||||
|
#define PH7 123 //1:I2C3_SCL
|
||||||
|
#define PH8 124 //1:I2C3_SDA
|
||||||
|
#define PH9 125 //1:TIM12_CH2
|
||||||
|
#define PH10 126 //1:TIM5_CH1
|
||||||
|
#define PH11 127 //1:TIM5_CH2
|
||||||
|
#define PH12 128 //1:TIM5_CH3
|
||||||
|
#define PH13 129
|
||||||
|
#define PH14 130
|
||||||
|
#define PH15 131
|
||||||
|
#define PI0 132 //1:TIM5_CH4 / SPI2_NSS
|
||||||
|
#define PI1 133 //1:SPI2_SCK
|
||||||
|
#define PI2 134 //1:TIM8_CH4 /SPI2_MISO
|
||||||
|
#define PI3 135 //1:SPI2_MOS
|
||||||
|
#define PI4 136
|
||||||
|
#define PI5 137 //1:TIM8_CH1
|
||||||
|
#define PI6 138 //1:TIM8_CH2
|
||||||
|
#define PI7 139 //1:TIM8_CH3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
// This must be a literal
|
||||||
|
#define NUM_DIGITAL_PINS (STM32F4X_GPIO_NUM + STM32F4X_ADC_NUM)
|
||||||
|
// This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS
|
||||||
|
#define NUM_ANALOG_INPUTS (STM32F4X_ADC_NUM)
|
||||||
|
#define NUM_ANALOG_FIRST (STM32F4X_GPIO_NUM)
|
||||||
|
|
||||||
|
// Below ADC, DAC and PWM definitions already done in the core
|
||||||
|
// Could be redefined here if needed
|
||||||
|
// ADC resolution is 12bits
|
||||||
|
//#define ADC_RESOLUTION 12
|
||||||
|
//#define DACC_RESOLUTION 12
|
||||||
|
|
||||||
|
// PWM resolution
|
||||||
|
#define PWM_RESOLUTION 8
|
||||||
|
#define PWM_FREQUENCY 20000
|
||||||
|
#define PWM_MAX_DUTY_CYCLE 255
|
||||||
|
|
||||||
|
// Below SPI and I2C definitions already done in the core
|
||||||
|
// Could be redefined here if differs from the default one
|
||||||
|
// SPI Definitions
|
||||||
|
#define PIN_SPI_MOSI PB15
|
||||||
|
#define PIN_SPI_MISO PB14
|
||||||
|
#define PIN_SPI_SCK PB13
|
||||||
|
#define PIN_SPI_SS PB12
|
||||||
|
|
||||||
|
// I2C Definitions
|
||||||
|
#define PIN_WIRE_SDA PB7
|
||||||
|
#define PIN_WIRE_SCL PB6
|
||||||
|
|
||||||
|
// Timer Definitions
|
||||||
|
//Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c
|
||||||
|
#define TIMER_TONE TIM6
|
||||||
|
|
||||||
|
// Do not use basic timer: OC is required
|
||||||
|
#define TIMER_SERVO TIM2 //TODO: advanced-control timers don't work
|
||||||
|
|
||||||
|
// UART Definitions
|
||||||
|
// Define here Serial instance number to map on Serial generic name
|
||||||
|
#define SERIAL_UART_INSTANCE 1 //ex: 2 for Serial2 (USART2)
|
||||||
|
// DEBUG_UART could be redefined to print on another instance than 'Serial'
|
||||||
|
//#define DEBUG_UART ((USART_TypeDef *) U(S)ARTX) // ex: USART3
|
||||||
|
// DEBUG_UART baudrate, default: 9600 if not defined
|
||||||
|
//#define DEBUG_UART_BAUDRATE x
|
||||||
|
// DEBUG_UART Tx pin name, default: the first one found in PinMap_UART_TX for DEBUG_UART
|
||||||
|
//#define DEBUG_PINNAME_TX PX_n // PinName used for TX
|
||||||
|
|
||||||
|
// Default pin used for 'Serial' instance (ex: ST-Link)
|
||||||
|
// Mandatory for Firmata
|
||||||
|
#define PIN_SERIAL_RX PA10
|
||||||
|
#define PIN_SERIAL_TX PA9
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
} // extern "C"
|
||||||
|
#endif
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
* Arduino objects - C++ only
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
// These serial port names are intended to allow libraries and architecture-neutral
|
||||||
|
// sketches to automatically default to the correct port name for a particular type
|
||||||
|
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
|
||||||
|
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
|
||||||
|
//
|
||||||
|
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
|
||||||
|
//
|
||||||
|
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
|
||||||
|
//
|
||||||
|
// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
|
||||||
|
//
|
||||||
|
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
|
||||||
|
//
|
||||||
|
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
|
||||||
|
// pins are NOT connected to anything by default.
|
||||||
|
#define SERIAL_PORT_MONITOR Serial
|
||||||
|
#define SERIAL_PORT_HARDWARE Serial1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _VARIANT_ARDUINO_STM32_ */
|
||||||
Loading…
Reference in New Issue