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@ -65,159 +65,161 @@ extern const PinName digitalPin[];
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#if STM32F4X_PIN_NUM >= 64 //64 pins mcu, 51 gpio
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#define PC13 0
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#define PC14 1 //OSC32_IN
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#define PC15 2 //OSC32_OUT
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#define PH0 3 //OSC_IN
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#define PH1 4 //OSC_OUT
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#define PC0 5 //1: 2:ADC123_IN10
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#define PC1 6 //1: 2:ADC123_IN11
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#define PC2 7 //1:SPI2_MISO 2:ADC123_IN12
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#define PC3 8 //1:SPI2_MOSI 2:ADC123_IN13
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#define PA0 9 //1:UART4_TX / TIM5_CH1 2:ADC123_IN0
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#define PA1 10 //1:UART4_RX / TIM5_CH2 / TIM2_CH2 2:ADC123_IN1
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#define PA2 11 //1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3 2:ADC123_IN2
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#define PA3 12 //1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4 2:ADC123_IN3
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#define PA4 13 //NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK 2:ADC12_IN4 / DAC_OUT1
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#define PA5 14 //NOT FT 1:SPI1_SCK 2:ADC12_IN5 / DAC_OUT2
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#define PA6 15 //1:SPI1_MISO / TIM13_CH1 / TIM3_CH1 2:ADC12_IN6
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#define PA7 16 //1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2 2:ADC12_IN7
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#define PC4 17 //1: 2:ADC12_IN14
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#define PC5 18 //1: 2:ADC12_IN15
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#define PB0 19 //1:TIM3_CH3 2:ADC12_IN8
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#define PB1 20 //1:TIM3_CH4 2:ADC12_IN9
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#define PB2 21 //BOOT1
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#define PB10 22 //1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
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#define PB11 23 //1:I2C2_SDA / USART3_RX / TIM2_CH4
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#define PB12 24 //1:SPI2_NSS / OTG_HS_ID
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#define PB13 25 //1:SPI2_SCK 2:OTG_HS_VBUS
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#define PB14 26 //1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
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#define PB15 27 //SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
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#define PC6 28 //1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
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#define PC7 29 //1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
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#define PC8 30 //1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
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#define PC9 31 //1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
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#define PA8 32 //1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
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#define PA9 33 //1:USART1_TX / TIM1_CH2 2:OTG_FS_VBUS
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#define PA10 34 //1:USART1_RX / TIM1_CH3 / OTG_FS_ID
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#define PA11 35 //1:TIM1_CH4 / OTG_FS_DM
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#define PA12 36 //1:OTG_FS_DP
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#define PA13 37 //0:JTMS-SWDIO
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#define PA14 38 //0:JTCK-SWCLK
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#define PA15 39 //0:JTDI 1:SPI3_NSS / SPI1_NSS
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#define PC10 40 //1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
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#define PC11 41 //1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
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#define PC12 42 //1:UART5_TX / SPI3_MOSI / SDIO_CK
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#define PD2 43 //1:UART5_RX / SDIO_CMD
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#define PB3 44 //0:JTDO 1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
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#define PB4 45 //0:NJTRST 1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
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#define PB5 46 //1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
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#define PB6 47 //1:I2C1_SCL / TIM4_CH1 / USART1_TX
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#define PB7 48 //1:I2C1_SDA / TIM4_CH2 / USART1_RX
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#define PB8 49 //1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
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#define PB9 50 //1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
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#define PC14 1 //OSC32_IN
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#define PC15 2 //OSC32_OUT
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#define PH0 3 //OSC_IN
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#define PH1 4 //OSC_OUT
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#define PB2 5 //BOOT1
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#define PB10 6 //1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
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#define PB11 7 //1:I2C2_SDA / USART3_RX / TIM2_CH4
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#define PB12 8 //1:SPI2_NSS / OTG_HS_ID
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#define PB13 9 //1:SPI2_SCK 2:OTG_HS_VBUS
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#define PB14 10 //1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
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#define PB15 11 //SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
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#define PC6 12 //1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
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#define PC7 13 //1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
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#define PC8 14 //1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
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#define PC9 15 //1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
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#define PA8 16 //1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
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#define PA9 17 //1:USART1_TX / TIM1_CH2 2:OTG_FS_VBUS
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#define PA10 18 //1:USART1_RX / TIM1_CH3 / OTG_FS_ID
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#define PA11 19 //1:TIM1_CH4 / OTG_FS_DM
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#define PA12 20 //1:OTG_FS_DP
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#define PA13 21 //0:JTMS-SWDIO
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#define PA14 22 //0:JTCK-SWCLK
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#define PA15 23 //0:JTDI 1:SPI3_NSS / SPI1_NSS
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#define PC10 24 //1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
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#define PC11 25 //1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
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#define PC12 26 //1:UART5_TX / SPI3_MOSI / SDIO_CK
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#define PD2 27 //1:UART5_RX / SDIO_CMD
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#define PB3 28 //0:JTDO 1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
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#define PB4 29 //0:NJTRST 1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
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#define PB5 30 //1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
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#define PB6 31 //1:I2C1_SCL / TIM4_CH1 / USART1_TX
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#define PB7 32 //1:I2C1_SDA / TIM4_CH2 / USART1_RX
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#define PB8 33 //1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
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#define PB9 34 //1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
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#define PA0 35 //1:UART4_TX / TIM5_CH1 2:ADC123_IN0
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#define PA1 36 //1:UART4_RX / TIM5_CH2 / TIM2_CH2 2:ADC123_IN1
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#define PA2 37 //1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3 2:ADC123_IN2
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#define PA3 38 //1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4 2:ADC123_IN3
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#define PA4 39 //NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK 2:ADC12_IN4 / DAC_OUT1
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#define PA5 40 //NOT FT 1:SPI1_SCK 2:ADC12_IN5 / DAC_OUT2
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#define PA6 41 //1:SPI1_MISO / TIM13_CH1 / TIM3_CH1 2:ADC12_IN6
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#define PA7 42 //1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2 2:ADC12_IN7
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#define PB0 43 //1:TIM3_CH3 2:ADC12_IN8
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#define PB1 44 //1:TIM3_CH4 2:ADC12_IN9
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#define PC0 45 //1: 2:ADC123_IN10
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#define PC1 46 //1: 2:ADC123_IN11
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#define PC2 47 //1:SPI2_MISO 2:ADC123_IN12
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#define PC3 48 //1:SPI2_MOSI 2:ADC123_IN13
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#define PC4 49 //1: 2:ADC12_IN14
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#define PC5 50 //1: 2:ADC12_IN15
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#if STM32F4X_PIN_NUM >= 144
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#define PF3 51 //1:FSMC_A3 2:ADC3_IN9
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#define PF4 52 //1:FSMC_A4 2:ADC3_IN14
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#define PF5 53 //1:FSMC_A5 2:ADC3_IN15
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#define PF6 54 //1:TIM10_CH1 2:ADC3_IN4
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#define PF7 55 //1:TIM11_CH1 2:ADC3_IN5
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#define PF8 56 //1:TIM13_CH1 2:ADC3_IN6
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#define PF9 57 //1;TIM14_CH1 2:ADC3_IN7
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#define PF10 58 //2:ADC3_IN8
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#endif
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#endif
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#if STM32F4X_PIN_NUM >= 100 //100 pins mcu, 82 gpio
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#define PE2 51 //1:FSMC_A23
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#define PE3 52 //1:FSMC_A19
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#define PE4 53 //1:FSMC_A20
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#define PE5 54 //1:FSMC_A21
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#define PE6 55 //1:FSMC_A22
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#define PE7 56 //1:FSMC_D4
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#define PE8 57 //1:FSMC_D5
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#define PE9 58 //1:FSMC_D6 / TIM1_CH1
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#define PE10 59 //1:FSMC_D7
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#define PE11 60 //1:FSMC_D8 / TIM1_CH2
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#define PE12 61 //1:FSMC_D9
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#define PE13 62 //1:FSMC_D10 / TIM1_CH3
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#define PE14 63 //1:FSMC_D11 / TIM1_CH4
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#define PE15 64 //1:FSMC_D12
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#define PD8 65 //1:FSMC_D13 / USART3_TX
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#define PD9 66 //1:FSMC_D14 / USART3_RX
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#define PD10 67 //1:FSMC_D15
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#define PD11 68 //1:FSMC_A16
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#define PD12 69 //1:FSMC_A17 / TIM4_CH1
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#define PD13 70 //1:FSMC_A18 / TIM4_CH2
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#define PD14 71 //1:FSMC_D0 / TIM4_CH3
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#define PD15 72 //1:FSMC_D1 / TIM4_CH4
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#define PD0 73 //1:FSMC_D2
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#define PD1 74 //1:FSMC_D3
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#define PD3 75 //1:FSMC_CLK
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#define PD4 76 //1:FSMC_NOE
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#define PD5 77 //1:USART2_TX
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#define PD6 78 //1:USART2_RX
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#define PD7 79
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#define PE0 80
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#define PE1 81
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#define PE2 (35+STM32F4X_ADC_NUM) //1:FSMC_A23
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#define PE3 (36+STM32F4X_ADC_NUM) //1:FSMC_A19
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#define PE4 (37+STM32F4X_ADC_NUM) //1:FSMC_A20
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#define PE5 (38+STM32F4X_ADC_NUM) //1:FSMC_A21
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#define PE6 (39+STM32F4X_ADC_NUM) //1:FSMC_A22
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#define PE7 (40+STM32F4X_ADC_NUM) //1:FSMC_D4
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#define PE8 (41+STM32F4X_ADC_NUM) //1:FSMC_D5
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#define PE9 (42+STM32F4X_ADC_NUM) //1:FSMC_D6 / TIM1_CH1
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#define PE10 (43+STM32F4X_ADC_NUM) //1:FSMC_D7
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#define PE11 (44+STM32F4X_ADC_NUM) //1:FSMC_D8 / TIM1_CH2
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#define PE12 (45+STM32F4X_ADC_NUM) //1:FSMC_D9
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#define PE13 (46+STM32F4X_ADC_NUM) //1:FSMC_D10 / TIM1_CH3
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#define PE14 (47+STM32F4X_ADC_NUM) //1:FSMC_D11 / TIM1_CH4
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#define PE15 (48+STM32F4X_ADC_NUM) //1:FSMC_D12
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#define PD8 (49+STM32F4X_ADC_NUM) //1:FSMC_D13 / USART3_TX
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#define PD9 (50+STM32F4X_ADC_NUM) //1:FSMC_D14 / USART3_RX
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#define PD10 (51+STM32F4X_ADC_NUM) //1:FSMC_D15
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#define PD11 (52+STM32F4X_ADC_NUM) //1:FSMC_A16
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#define PD12 (53+STM32F4X_ADC_NUM) //1:FSMC_A17 / TIM4_CH1
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#define PD13 (54+STM32F4X_ADC_NUM) //1:FSMC_A18 / TIM4_CH2
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#define PD14 (55+STM32F4X_ADC_NUM) //1:FSMC_D0 / TIM4_CH3
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#define PD15 (56+STM32F4X_ADC_NUM) //1:FSMC_D1 / TIM4_CH4
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#define PD0 (57+STM32F4X_ADC_NUM) //1:FSMC_D2
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#define PD1 (58+STM32F4X_ADC_NUM) //1:FSMC_D3
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#define PD3 (59+STM32F4X_ADC_NUM) //1:FSMC_CLK
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#define PD4 (60+STM32F4X_ADC_NUM) //1:FSMC_NOE
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#define PD5 (61+STM32F4X_ADC_NUM) //1:USART2_TX
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#define PD6 (62+STM32F4X_ADC_NUM) //1:USART2_RX
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#define PD7 (63+STM32F4X_ADC_NUM)
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#define PE0 (64+STM32F4X_ADC_NUM)
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#define PE1 (65+STM32F4X_ADC_NUM)
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#endif
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#if STM32F4X_PIN_NUM >= 144 //144 pins mcu, 114 gpio
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#define PF0 82 //1:FSMC_A0 / I2C2_SDA
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#define PF1 83 //1:FSMC_A1 / I2C2_SCL
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#define PF2 84 //1:FSMC_A2
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#define PF3 85 //1:FSMC_A3 2:ADC3_IN9
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#define PF4 86 //1:FSMC_A4 2:ADC3_IN14
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#define PF5 87 //1:FSMC_A5 2:ADC3_IN15
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#define PF6 88 //1:TIM10_CH1 2:ADC3_IN4
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#define PF7 89 //1:TIM11_CH1 2:ADC3_IN5
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#define PF8 90 //1:TIM13_CH1 2:ADC3_IN6
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#define PF9 91 //1;TIM14_CH1 2:ADC3_IN7
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#define PF10 92 //2:ADC3_IN8
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#define PF11 93
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#define PF12 94 //1:FSMC_A6
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#define PF13 95 //1:FSMC_A7
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#define PF14 96 //1:FSMC_A8
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#define PF15 97 //1:FSMC_A9
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#define PG0 98 //1:FSMC_A10
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#define PG1 99 //1:FSMC_A11
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#define PG2 100 //1:FSMC_A12
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#define PG3 101 //1:FSMC_A13
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#define PG4 102 //1:FSMC_A14
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#define PG5 103 //1:FSMC_A15
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#define PG6 104
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#define PG7 105
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#define PG8 106
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#define PG9 107 //1:USART6_RX
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#define PG10 108 //1:FSMC_NE3
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#define PG11 109
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#define PG12 110 //1:FSMC_NE4
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#define PG13 111 //1:FSMC_A24
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#define PG14 112 //1:FSMC_A25 / USART6_TX
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#define PG15 113
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#define PF0 (66+STM32F4X_ADC_NUM) //1:FSMC_A0 / I2C2_SDA
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#define PF1 (67+STM32F4X_ADC_NUM) //1:FSMC_A1 / I2C2_SCL
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#define PF2 (68+STM32F4X_ADC_NUM) //1:FSMC_A2
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#define PF11 (69+STM32F4X_ADC_NUM)
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#define PF12 (70+STM32F4X_ADC_NUM) //1:FSMC_A6
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#define PF13 (71+STM32F4X_ADC_NUM) //1:FSMC_A7
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#define PF14 (72+STM32F4X_ADC_NUM) //1:FSMC_A8
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#define PF15 (73+STM32F4X_ADC_NUM) //1:FSMC_A9
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#define PG0 (74+STM32F4X_ADC_NUM) //1:FSMC_A10
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#define PG1 (75+STM32F4X_ADC_NUM) //1:FSMC_A11
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#define PG2 (76+STM32F4X_ADC_NUM) //1:FSMC_A12
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#define PG3 (77+STM32F4X_ADC_NUM) //1:FSMC_A13
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#define PG4 (78+STM32F4X_ADC_NUM) //1:FSMC_A14
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#define PG5 (79+STM32F4X_ADC_NUM) //1:FSMC_A15
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#define PG6 (80+STM32F4X_ADC_NUM)
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#define PG7 (81+STM32F4X_ADC_NUM)
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#define PG8 (82+STM32F4X_ADC_NUM)
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#define PG9 (83+STM32F4X_ADC_NUM) //1:USART6_RX
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#define PG10 (84+STM32F4X_ADC_NUM) //1:FSMC_NE3
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#define PG11 (85+STM32F4X_ADC_NUM)
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#define PG12 (86+STM32F4X_ADC_NUM) //1:FSMC_NE4
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#define PG13 (87+STM32F4X_ADC_NUM) //1:FSMC_A24
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#define PG14 (88+STM32F4X_ADC_NUM) //1:FSMC_A25 / USART6_TX
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#define PG15 (89+STM32F4X_ADC_NUM)
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#endif
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#if STM32F4X_PIN_NUM >= 176 //176 pins mcu, 140 gpio
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#define PI8 114
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#define PI9 115
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#define PI10 116
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#define PI11 117
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#define PH2 118
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#define PH3 119
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#define PH4 120 //1:I2C2_SCL
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#define PH5 121 //1:I2C2_SDA
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#define PH6 122 //1:TIM12_CH1
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#define PH7 123 //1:I2C3_SCL
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#define PH8 124 //1:I2C3_SDA
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#define PH9 125 //1:TIM12_CH2
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#define PH10 126 //1:TIM5_CH1
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#define PH11 127 //1:TIM5_CH2
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#define PH12 128 //1:TIM5_CH3
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#define PH13 129
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#define PH14 130
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#define PH15 131
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#define PI0 132 //1:TIM5_CH4 / SPI2_NSS
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#define PI1 133 //1:SPI2_SCK
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#define PI2 134 //1:TIM8_CH4 /SPI2_MISO
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#define PI3 135 //1:SPI2_MOS
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#define PI4 136
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#define PI5 137 //1:TIM8_CH1
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#define PI6 138 //1:TIM8_CH2
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#define PI7 139 //1:TIM8_CH3
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#define PI8 (90+STM32F4X_ADC_NUM)
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#define PI9 (91+STM32F4X_ADC_NUM)
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#define PI10 (92+STM32F4X_ADC_NUM)
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#define PI11 (93+STM32F4X_ADC_NUM)
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#define PH2 (94+STM32F4X_ADC_NUM)
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#define PH3 (95+STM32F4X_ADC_NUM)
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#define PH4 (96+STM32F4X_ADC_NUM) //1:I2C2_SCL
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#define PH5 (97+STM32F4X_ADC_NUM) //1:I2C2_SDA
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#define PH6 (98+STM32F4X_ADC_NUM) //1:TIM12_CH1
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#define PH7 (99+STM32F4X_ADC_NUM) //1:I2C3_SCL
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#define PH8 (100+STM32F4X_ADC_NUM) //1:I2C3_SDA
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#define PH9 (101+STM32F4X_ADC_NUM) //1:TIM12_CH2
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#define PH10 (102+STM32F4X_ADC_NUM) //1:TIM5_CH1
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#define PH11 (103+STM32F4X_ADC_NUM) //1:TIM5_CH2
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#define PH12 (104+STM32F4X_ADC_NUM) //1:TIM5_CH3
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#define PH13 (105+STM32F4X_ADC_NUM)
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#define PH14 (106+STM32F4X_ADC_NUM)
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#define PH15 (107+STM32F4X_ADC_NUM)
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#define PI0 (108+STM32F4X_ADC_NUM) //1:TIM5_CH4 / SPI2_NSS
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#define PI1 (109+STM32F4X_ADC_NUM) //1:SPI2_SCK
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#define PI2 (110+STM32F4X_ADC_NUM) //1:TIM8_CH4 /SPI2_MISO
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#define PI3 (111+STM32F4X_ADC_NUM) //1:SPI2_MOS
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#define PI4 (112+STM32F4X_ADC_NUM)
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#define PI5 (113+STM32F4X_ADC_NUM) //1:TIM8_CH1
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#define PI6 (114+STM32F4X_ADC_NUM) //1:TIM8_CH2
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#define PI7 (115+STM32F4X_ADC_NUM) //1:TIM8_CH3
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#endif
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// This must be a literal
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#define NUM_DIGITAL_PINS (STM32F4X_GPIO_NUM + STM32F4X_ADC_NUM)
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#define NUM_DIGITAL_PINS (STM32F4X_GPIO_NUM)
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// This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS
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#define NUM_ANALOG_INPUTS (STM32F4X_ADC_NUM)
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#define NUM_ANALOG_FIRST (STM32F4X_GPIO_NUM)
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#define NUM_ANALOG_FIRST 35
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// Below ADC, DAC and PWM definitions already done in the core
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// Could be redefined here if needed
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BigTreeTech
5 years ago
committed by