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@ -58,6 +58,7 @@
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#include <U8glib.h>
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#include <Arduino.h>
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#include "../../core/macros.h"
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#include "../Delay.h"
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void u8g_SetPIOutput_DUE(u8g_t *u8g, uint8_t pin_index) {
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PIO_Configure(g_APinDescription[u8g->pin_list[pin_index]].pPort, PIO_OUTPUT_1,
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@ -71,28 +72,6 @@ void u8g_SetPILevel_DUE(u8g_t *u8g, uint8_t pin_index, uint8_t level) {
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else port->PIO_CODR = mask;
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}
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void __delay_4cycles(uint32_t cy) __attribute__ ((weak));
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FORCE_INLINE void __delay_4cycles(uint32_t cy) { // +1 cycle
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#if ARCH_PIPELINE_RELOAD_CYCLES<2
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#define EXTRA_NOP_CYCLES "nop"
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#else
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#define EXTRA_NOP_CYCLES ""
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#endif
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__asm__ __volatile__(
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".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
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L("loop%=")
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A("subs %[cnt],#1")
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A(EXTRA_NOP_CYCLES)
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A("bne loop%=")
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: [cnt]"+r"(cy) // output: +r means input+output
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: // input:
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: "cc" // clobbers:
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);
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}
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Pio *SCK_pPio, *MOSI_pPio;
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uint32_t SCK_dwMask, MOSI_dwMask;
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@ -102,9 +81,9 @@ static void spiSend_sw_DUE(uint8_t val) { // 800KHz
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MOSI_pPio->PIO_SODR = MOSI_dwMask;
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else
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MOSI_pPio->PIO_CODR = MOSI_dwMask;
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__delay_4cycles(1);
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DELAY_NS(48);
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SCK_pPio->PIO_SODR = SCK_dwMask;
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__delay_4cycles(19); // 16 dead, 17 garbage, 18/0 900kHz, 19/1 825k, 20/1 800k, 21/2 725KHz
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DELAY_NS(905); // 762 dead, 810 garbage, 858/0 900kHz, 905/1 825k, 953/1 800k, 1000/2 725KHz
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val <<= 1;
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SCK_pPio->PIO_CODR = SCK_dwMask;
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}
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@ -125,8 +104,7 @@ static void u8g_com_DUE_st7920_write_byte_sw_spi(uint8_t rs, uint8_t val) {
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/* data */
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spiSend_sw_DUE(0x0FA);
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for (i = 0; i < 4; i++) // give the controller some time to process the data
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u8g_10MicroDelay(); // 2 is bad, 3 is OK, 4 is safe
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DELAY_US(40); // give the controller some time to process the data: 20 is bad, 30 is OK, 40 is safe
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}
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spiSend_sw_DUE(val & 0x0F0);
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