PWM->PWM_WPCR=WPKEY|WPRG_ALL|WPCMD_DIS_SW;// enable setting of all PWM registers
PWM->PWM_CLK=PWM_CLOCK_F;// enable CLK_A and set it to 1MHz, leave CLK_B disabled
PWM->PWM_CH_NUM[0].PWM_CMR=0b1011;// set channel 0 to Clock A input & to left aligned
PWM->PWM_CH_NUM[1].PWM_CMR=0b1011;// set channel 1 to Clock A input & to left aligned
PWM->PWM_CH_NUM[2].PWM_CMR=0b1011;// set channel 2 to Clock A input & to left aligned
PWM->PWM_CH_NUM[3].PWM_CMR=0b1011;// set channel 3 to Clock A input & to left aligned
PWM->PWM_CH_NUM[4].PWM_CMR=0b1011;// set channel 4 to Clock A input & to left aligned
if(G2_PWM_X)PWM->PWM_CH_NUM[1].PWM_CMR=0b1011;// set channel 1 to Clock A input & to left aligned
if(G2_PWM_Y)PWM->PWM_CH_NUM[2].PWM_CMR=0b1011;// set channel 2 to Clock A input & to left aligned
if(G2_PWM_Z)PWM->PWM_CH_NUM[3].PWM_CMR=0b1011;// set channel 3 to Clock A input & to left aligned
if(G2_PWM_E)PWM->PWM_CH_NUM[4].PWM_CMR=0b1011;// set channel 4 to Clock A input & to left aligned
PWM->PWM_CH_NUM[0].PWM_CPRD=PWM_PERIOD_US;// set channel 0 Period
PWM->PWM_IER2=PWM_IER1_CHID0;// generate interrupt when counter0 overflows
PWM->PWM_IER2=PWM_IER2_CMPM0|PWM_IER2_CMPM1|PWM_IER2_CMPM2|PWM_IER2_CMPM3|PWM_IER2_CMPM4;// generate interrupt on compare event
PWM->PWM_CMP[1].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[0]));// interrupt when counter0 == CMPV - used to set Motor 1 PWM inactive
PWM->PWM_CMP[2].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[0]));// interrupt when counter0 == CMPV - used to set Motor 2 PWM inactive
PWM->PWM_CMP[3].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[1]));// interrupt when counter0 == CMPV - used to set Motor 3 PWM inactive
PWM->PWM_CMP[4].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[2]));// interrupt when counter0 == CMPV - used to set Motor 4 PWM inactive
PWM->PWM_SCM=PWM_SCM_UPDM_MODE0|PWM_SCM_SYNC0|PWM_SCM_SYNC1|PWM_SCM_SYNC2|PWM_SCM_SYNC3|PWM_SCM_SYNC4;// sync 1-4 with 0, use mode 0 for updates
PWM->PWM_ENA=PWM_ENA_CHID0|PWM_ENA_CHID1|PWM_ENA_CHID2|PWM_ENA_CHID3|PWM_ENA_CHID4;// enable the channels used by G2
PWM->PWM_IER1=PWM_IER1_CHID0|PWM_IER1_CHID1|PWM_IER1_CHID2|PWM_IER1_CHID3|PWM_IER1_CHID4;// enable interrupts for the channels used by G2
PWM->PWM_IER2=PWM_IER2_CMPM0
|G2_MASK_X(PWM_IER2_CMPM1)
|G2_MASK_Y(PWM_IER2_CMPM2)
|G2_MASK_Z(PWM_IER2_CMPM3)
|G2_MASK_E(PWM_IER2_CMPM4)
;// generate interrupt on compare event
if(G2_PWM_X)PWM->PWM_CMP[1].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[0]));// interrupt when counter0 == CMPV - used to set Motor 1 PWM inactive
if(G2_PWM_Y)PWM->PWM_CMP[2].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[0]));// interrupt when counter0 == CMPV - used to set Motor 2 PWM inactive
if(G2_PWM_Z)PWM->PWM_CMP[3].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[1]));// interrupt when counter0 == CMPV - used to set Motor 3 PWM inactive
if(G2_PWM_E)PWM->PWM_CMP[4].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[2]));// interrupt when counter0 == CMPV - used to set Motor 4 PWM inactive