From 20ebe218c8dc33e1ef025d708807ccabc60edea6 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Mon, 9 Oct 2017 17:01:07 -0500 Subject: [PATCH] Tweaks to VIKI lcd support --- .../lcd/dogm/ultralcd_st7565_u8glib_VIKI.h | 59 +++++++++---------- 1 file changed, 28 insertions(+), 31 deletions(-) diff --git a/Marlin/src/lcd/dogm/ultralcd_st7565_u8glib_VIKI.h b/Marlin/src/lcd/dogm/ultralcd_st7565_u8glib_VIKI.h index 41a0d5c07..a86238885 100644 --- a/Marlin/src/lcd/dogm/ultralcd_st7565_u8glib_VIKI.h +++ b/Marlin/src/lcd/dogm/ultralcd_st7565_u8glib_VIKI.h @@ -86,7 +86,6 @@ #define ST7565_DELAY_3 CPU_ST7565_DELAY_3 #endif - #if ENABLED(SHARED_SPI) // Re-ARM requires that the LCD and the SD card share a single SPI #define ST7565_WRITE_BYTE(a) { spiSend((uint8_t)a); U8G_DELAY; } @@ -129,8 +128,7 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) { switch (msg) { - case U8G_DEV_MSG_INIT: - { + case U8G_DEV_MSG_INIT: { OUT_WRITE(ST7565_CS_PIN, LOW); #if ENABLED(SHARED_SPI) u8g_Delay(250); @@ -149,52 +147,50 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg ST7565_NA0(); /* instruction mode */ ST7565_NCS(); /* enable chip */ - - ST7565_WRITE_BYTE(0x0A2); /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */ + ST7565_WRITE_BYTE(0x0A2); /* 0x0A2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */ ST7565_WRITE_BYTE(0x0A0); /* Normal ADC Select (according to Displaytech 64128N datasheet) */ - ST7565_WRITE_BYTE(0x0c8); /* common output mode: set scan direction normal operation/SHL Select; 0x0c0 --> SHL = 0; normal; 0x0c8 --> SHL = 1 */ + ST7565_WRITE_BYTE(0x0C8); /* common output mode: set scan direction normal operation/SHL Select; 0x0C0 --> SHL = 0; normal; 0x0C8 --> SHL = 1 */ ST7565_WRITE_BYTE(0x040); /* Display start line for Displaytech 64128N */ ST7565_WRITE_BYTE(0x028 | 0x04); /* power control: turn on voltage converter */ -// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */ + //U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */ ST7565_WRITE_BYTE(0x028 | 0x06); /* power control: turn on voltage regulator */ -// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */ + //U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */ ST7565_WRITE_BYTE(0x028 | 0x07); /* power control: turn on voltage follower */ -// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */ - + //U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */ ST7565_WRITE_BYTE(0x010); /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */ - ST7565_WRITE_BYTE(0x0a6); /* display normal, bit val 0: LCD pixel off. */ + ST7565_WRITE_BYTE(0x0A6); /* display normal, bit val 0: LCD pixel off. */ ST7565_WRITE_BYTE(0x081); /* set contrast */ - ST7565_WRITE_BYTE(0x01e); /* Contrast value. Setting for controlling brightness of Displaytech 64128N */ + ST7565_WRITE_BYTE(0x01E); /* Contrast value. Setting for controlling brightness of Displaytech 64128N */ - - ST7565_WRITE_BYTE(0x0af); /* display on */ + ST7565_WRITE_BYTE(0x0AF); /* display on */ U8G_ESC_DLY(100); /* delay 100 ms */ - ST7565_WRITE_BYTE(0x0a5); /* display all points; ST7565 */ + ST7565_WRITE_BYTE(0x0A5); /* display all points; ST7565 */ U8G_ESC_DLY(100); /* delay 100 ms */ U8G_ESC_DLY(100); /* delay 100 ms */ - ST7565_WRITE_BYTE(0x0a4); /* normal display */ + ST7565_WRITE_BYTE(0x0A4); /* normal display */ ST7565_CS(); /* disable chip */ } /* end of sequence */ - break; - case U8G_DEV_MSG_STOP: - break; - case U8G_DEV_MSG_PAGE_NEXT: - { u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem); + break; + + case U8G_DEV_MSG_STOP: break; + + case U8G_DEV_MSG_PAGE_NEXT: { + u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem); ST7565_CS(); /* disable chip */ ST7565_NA0(); /* instruction mode */ ST7565_NCS(); /* enable chip */ ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */ ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */ /* end of sequence */ - ST7565_WRITE_BYTE(0x0b0 | (2*pb->p.page));; /* select current page (ST7565R) */ + ST7565_WRITE_BYTE(0x0B0 | (2*pb->p.page));; /* select current page (ST7565R) */ ST7565_A0(); /* data mode */ ST7560_WriteSequence( (uint8_t) pb->width, (uint8_t *)pb->buf); ST7565_CS(); /* disable chip */ @@ -203,12 +199,13 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */ ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */ /* end of sequence */ - ST7565_WRITE_BYTE(0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */ + ST7565_WRITE_BYTE(0x0B0 | (2*pb->p.page+1)); /* select current page (ST7565R) */ ST7565_A0(); /* data mode */ ST7560_WriteSequence( (uint8_t) pb->width, (uint8_t *)(pb->buf)+pb->width); ST7565_CS(); /* disable chip */ } - break; + break; + case U8G_DEV_MSG_CONTRAST: ST7565_NCS(); ST7565_NA0(); /* instruction mode */ @@ -216,21 +213,23 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg ST7565_WRITE_BYTE((*(uint8_t *)arg) >> 2); ST7565_CS(); /* disable chip */ return 1; + case U8G_DEV_MSG_SLEEP_ON: ST7565_NA0(); /* instruction mode */ ST7565_NCS(); /* enable chip */ - ST7565_WRITE_BYTE(0x0ac); /* static indicator off */ + ST7565_WRITE_BYTE(0x0AC); /* static indicator off */ ST7565_WRITE_BYTE(0x000); /* indicator register set (not sure if this is required) */ - ST7565_WRITE_BYTE(0x0ae); /* display off */ - ST7565_WRITE_BYTE(0x0a5); /* all points on */ + ST7565_WRITE_BYTE(0x0AE); /* display off */ + ST7565_WRITE_BYTE(0x0A5); /* all points on */ ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */ /* end of sequence */ return 1; + case U8G_DEV_MSG_SLEEP_OFF: ST7565_NA0(); /* instruction mode */ ST7565_NCS(); /* enable chip */ - ST7565_WRITE_BYTE(0x0a4); /* all points off */ - ST7565_WRITE_BYTE(0x0af); /* display on */ + ST7565_WRITE_BYTE(0x0A4); /* all points off */ + ST7565_WRITE_BYTE(0x0AF); /* display on */ U8G_ESC_DLY(50); /* delay 50 ms */ ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */ /* end of sequence */ @@ -254,8 +253,6 @@ class U8GLIB_ST7565_64128n_2x_VIKI : public U8GLIB { { } }; - - #pragma GCC reset_options #endif // U8GLIB_ST7565